chaitanya.531
Member level 1
hi
plz help
when i synthesis vhdl
the following warnings occurs
Loading device for application Rf_Device from file '4vfx12.nph' in environment C:\Xilinx.
WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: rc5round_ao<15>_cyo, ao<32>, rc5round_ao<30>_cyo, c1/dec/d4<16>, c1/dec/d3<25>, rc5round_ao<28>_cyo, rc5round_ao<4>_cyo, rc5round_ao<29>_cyo, rc5round_ao<12>_cyo, rc5round_ao<14>_cyo, c1/dec/d2<28>, m1<32>, rc5round_ao<18>_cyo, ao<31>, rc5round_ao<25>_cyo, rc5round_ao<27>_cyo, rc5round_ao<22>_cyo, rc5round_ao<5>_cyo, cs<1>, rc5round_ao<2>_cyo, rc5round_ao<3>_cyo, rc5round_ao<26>_cyo, rc5round_ao<21>_cyo, rc5round_ao<11>_cyo, rc5round_ao<23>_cyo, rc5round_ao<6>_cyo, rc5round_ao<24>_cyo, c1/dec/d4<17>, rc5round_ao<31>_cyo, rc5round_ao<17>_cyo, c1/dec/d2<29>, m2<32>, c1/dec/d1<31>, rc5round_ao<8>_cyo, rc5round_ao<19>_cyo, rc5round_ao<20>_cyo, rc5round_ao<10>_cyo, c1/dec/d3<24>, cs<32>, rc5round_ao<9>_cyo, m3<1>, rc5round_ao<16>_cyo,
m4<32>, rc5round_ao<13>_cyo, xo<32>, m2<31>, rc5round_ao<1>_cyo, rc5round_ao<7>_cyo, c1/dec/d1<30>.
WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: c1/dec/d3<17>, c1/dec/d4<2>, N22, ao<10>, ao<18>, c1/dec/d1<13>, ao<26>, cs<9>, m3<5>, cs<17>, c1/dec/d3<14>, N27, c1/dec/d2<19>, m3<13>, N23, N20, c1/dec/d2<27>, cs<25>, c1/dec/d3<11>, m1<31>, m2<7>, m3<21>, c1/dec/d4<23>, c1/dec/d1<2>, N29, c1/dec/d3<26>, m2<15>, m3<29>, c1/dec/d4<11>, N25, m2<23>, c1/dec/d4<26>, c1/dec/d1<5>, N28, N24, ao<9>, N32, c1/dec/d3<23>, ao<17>, N12, c1/dec/d3<20>, ao<25>, c1/dec/d4<32>, cs<8>, N18, c1/dec/d1<23>, c1/dec/d2<16>, c1/dec/d4<20>, m3<4>, c1/dec/d2<3>, c1/dec/d1<7>, cs<16>, m3<12>, c1/dec/d3<3>, cs<24>, m2<6>, m3<20>, N13, c1/dec/d4<3>, m2<14>, m3<28>, m2<22>, c1/dec/d3<32>, c1/dec/d1<14>, m2<30>, c1/dec/d3<29>, c1/dec/d3<9>, c1/dec/d1<28>, N14, ao<8>, c1/dec/d4<29>,
c1/dec/d2<31>, c1/dec/d1<18>, ao<16>, c1/dec/d3<12>, c1/dec/d1<26>, ao<24>, N10, cs<7>, c1/dec/d2<15>, c1/dec/d4<12>, m3<3>, cs<15>, c1/dec/d4<9>, m3<11>, c1/dec/d2<9>, cs<23>, c1/dec/d1<6>, m2<5>, m3<19>, c1/dec/d2<6>, cs<31>, c1/dec/d3<18>, m2<13>, m3<27>, N11, c1/dec/d3<6>, m2<21>, N4, m2<29>, c1/dec/d3<21>, c1/dec/d4<6>, c1/dec/d4<21>, ao<7>, c1/dec/d1<8>, c1/dec/d2<22>, c1/dec/d4<18>, ao<15>, c1/dec/d2<12>, ao<23>, c1/dec/d1<11>, c1/dec/d2<25>, cs<6>, c1/dec/d3<27>, m3<2>, cs<14>, c1/dec/d3<15>, m3<10>, cs<22>, m2<4>, c1/dec/d3<30>, m3<18>, c1/dec/d4<15>, cs<30>, m2<12>, m3<26>, c1/dec/d4<30>, c1/dec/d2<32>, m2<20>, c1/dec/d2<18>, c1/dec/d4<27>, m2<28>, c1/dec/d1<3>, c1/dec/d2<4>, ao<6>, ao<14>, N17, c1/dec/d1<16>, c1/dec/d2<21>, c1/dec/d4<24>, c1/dec/d2<7>, ao<22>, cs<5>, c1/dec/d1<24>,
ao<30>, c1/dec/d3<7>, cs<13>, m3<9>, N9, c1/dec/d3<4>, cs<21>, m2<3>, m3<17>, cs<29>, c1/dec/d4<4>, m2<11>, m3<25>, c1/dec/d1<29>, m2<19>, c1/dec/d2<1>, m2<27>, c1/dec/d1<21>, c1/dec/d3<1>, c1/dec/d1<12>, c1/dec/d2<26>, N5, ao<5>, c1/dec/d3<16>, c1/dec/d4<1>, N16, c1/dec/d1<19>, ao<13>, c1/dec/d3<13>, ao<21>, cs<4>, c1/dec/d4<13>, ao<29>, N8, cs<12>, N6, m3<8>, c1/dec/d2<10>, cs<20>, m2<2>, m3<16>, cs<28>, c1/dec/d1<4>, c1/dec/d3<10>, c1/dec/d2<14>, m2<10>, m3<24>, N21, c1/dec/d4<10>, c1/dec/d1<27>, m2<18>, N19, c1/dec/d4<7>, c1/dec/d3<22>, m2<26>, c1/dec/d4<22>, ao<4>, c1/dec/d2<17>, ao<12>, xo<31>, N15, ao<20>, cs<3>, c1/dec/d1<15>, c1/dec/d3<19>, ao<28>, c1/dec/d1<9>, c1/dec/d2<23>, cs<11>, c1/dec/d4<19>, c1/dec/d2<2>, m3<7>, cs<19>, c1/dec/d3<31>, m3<15>, N7, cs<27>, N31, m2<9>, m3<23>,
c1/dec/d4<31>, m2<17>, m2<25>, c1/dec/d3<28>, ao<3>, c1/dec/d1<1>, c1/dec/d2<11>, c1/dec/d4<28>, ao<11>, c1/dec/d1<17>, c1/dec/d4<25>, c1/dec/d2<8>, ao<19>, cs<2>, c1/dec/d4<5>, c1/dec/d1<25>, ao<27>, c1/dec/d3<8>, cs<10>, m3<6>, cs<18>, c1/dec/d4<8>, c1/dec/d1<22>, c1/dec/d2<20>, m3<14>, cs<26>, m2<8>, m3<22>, c1/dec/d2<5>, m2<16>, m3<30>, c1/dec/d3<5>, N30, m2<24>, N26, c1/dec/d3<2>, m4<31>, c1/dec/d1<20>, c1/dec/d4<14>, c1/dec/d2<13>, ao<2>, c1/dec/d1<10>, c1/dec/d2<24>.
the code is
plz help
when i synthesis vhdl
the following warnings occurs
Loading device for application Rf_Device from file '4vfx12.nph' in environment C:\Xilinx.
WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: rc5round_ao<15>_cyo, ao<32>, rc5round_ao<30>_cyo, c1/dec/d4<16>, c1/dec/d3<25>, rc5round_ao<28>_cyo, rc5round_ao<4>_cyo, rc5round_ao<29>_cyo, rc5round_ao<12>_cyo, rc5round_ao<14>_cyo, c1/dec/d2<28>, m1<32>, rc5round_ao<18>_cyo, ao<31>, rc5round_ao<25>_cyo, rc5round_ao<27>_cyo, rc5round_ao<22>_cyo, rc5round_ao<5>_cyo, cs<1>, rc5round_ao<2>_cyo, rc5round_ao<3>_cyo, rc5round_ao<26>_cyo, rc5round_ao<21>_cyo, rc5round_ao<11>_cyo, rc5round_ao<23>_cyo, rc5round_ao<6>_cyo, rc5round_ao<24>_cyo, c1/dec/d4<17>, rc5round_ao<31>_cyo, rc5round_ao<17>_cyo, c1/dec/d2<29>, m2<32>, c1/dec/d1<31>, rc5round_ao<8>_cyo, rc5round_ao<19>_cyo, rc5round_ao<20>_cyo, rc5round_ao<10>_cyo, c1/dec/d3<24>, cs<32>, rc5round_ao<9>_cyo, m3<1>, rc5round_ao<16>_cyo,
m4<32>, rc5round_ao<13>_cyo, xo<32>, m2<31>, rc5round_ao<1>_cyo, rc5round_ao<7>_cyo, c1/dec/d1<30>.
WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: c1/dec/d3<17>, c1/dec/d4<2>, N22, ao<10>, ao<18>, c1/dec/d1<13>, ao<26>, cs<9>, m3<5>, cs<17>, c1/dec/d3<14>, N27, c1/dec/d2<19>, m3<13>, N23, N20, c1/dec/d2<27>, cs<25>, c1/dec/d3<11>, m1<31>, m2<7>, m3<21>, c1/dec/d4<23>, c1/dec/d1<2>, N29, c1/dec/d3<26>, m2<15>, m3<29>, c1/dec/d4<11>, N25, m2<23>, c1/dec/d4<26>, c1/dec/d1<5>, N28, N24, ao<9>, N32, c1/dec/d3<23>, ao<17>, N12, c1/dec/d3<20>, ao<25>, c1/dec/d4<32>, cs<8>, N18, c1/dec/d1<23>, c1/dec/d2<16>, c1/dec/d4<20>, m3<4>, c1/dec/d2<3>, c1/dec/d1<7>, cs<16>, m3<12>, c1/dec/d3<3>, cs<24>, m2<6>, m3<20>, N13, c1/dec/d4<3>, m2<14>, m3<28>, m2<22>, c1/dec/d3<32>, c1/dec/d1<14>, m2<30>, c1/dec/d3<29>, c1/dec/d3<9>, c1/dec/d1<28>, N14, ao<8>, c1/dec/d4<29>,
c1/dec/d2<31>, c1/dec/d1<18>, ao<16>, c1/dec/d3<12>, c1/dec/d1<26>, ao<24>, N10, cs<7>, c1/dec/d2<15>, c1/dec/d4<12>, m3<3>, cs<15>, c1/dec/d4<9>, m3<11>, c1/dec/d2<9>, cs<23>, c1/dec/d1<6>, m2<5>, m3<19>, c1/dec/d2<6>, cs<31>, c1/dec/d3<18>, m2<13>, m3<27>, N11, c1/dec/d3<6>, m2<21>, N4, m2<29>, c1/dec/d3<21>, c1/dec/d4<6>, c1/dec/d4<21>, ao<7>, c1/dec/d1<8>, c1/dec/d2<22>, c1/dec/d4<18>, ao<15>, c1/dec/d2<12>, ao<23>, c1/dec/d1<11>, c1/dec/d2<25>, cs<6>, c1/dec/d3<27>, m3<2>, cs<14>, c1/dec/d3<15>, m3<10>, cs<22>, m2<4>, c1/dec/d3<30>, m3<18>, c1/dec/d4<15>, cs<30>, m2<12>, m3<26>, c1/dec/d4<30>, c1/dec/d2<32>, m2<20>, c1/dec/d2<18>, c1/dec/d4<27>, m2<28>, c1/dec/d1<3>, c1/dec/d2<4>, ao<6>, ao<14>, N17, c1/dec/d1<16>, c1/dec/d2<21>, c1/dec/d4<24>, c1/dec/d2<7>, ao<22>, cs<5>, c1/dec/d1<24>,
ao<30>, c1/dec/d3<7>, cs<13>, m3<9>, N9, c1/dec/d3<4>, cs<21>, m2<3>, m3<17>, cs<29>, c1/dec/d4<4>, m2<11>, m3<25>, c1/dec/d1<29>, m2<19>, c1/dec/d2<1>, m2<27>, c1/dec/d1<21>, c1/dec/d3<1>, c1/dec/d1<12>, c1/dec/d2<26>, N5, ao<5>, c1/dec/d3<16>, c1/dec/d4<1>, N16, c1/dec/d1<19>, ao<13>, c1/dec/d3<13>, ao<21>, cs<4>, c1/dec/d4<13>, ao<29>, N8, cs<12>, N6, m3<8>, c1/dec/d2<10>, cs<20>, m2<2>, m3<16>, cs<28>, c1/dec/d1<4>, c1/dec/d3<10>, c1/dec/d2<14>, m2<10>, m3<24>, N21, c1/dec/d4<10>, c1/dec/d1<27>, m2<18>, N19, c1/dec/d4<7>, c1/dec/d3<22>, m2<26>, c1/dec/d4<22>, ao<4>, c1/dec/d2<17>, ao<12>, xo<31>, N15, ao<20>, cs<3>, c1/dec/d1<15>, c1/dec/d3<19>, ao<28>, c1/dec/d1<9>, c1/dec/d2<23>, cs<11>, c1/dec/d4<19>, c1/dec/d2<2>, m3<7>, cs<19>, c1/dec/d3<31>, m3<15>, N7, cs<27>, N31, m2<9>, m3<23>,
c1/dec/d4<31>, m2<17>, m2<25>, c1/dec/d3<28>, ao<3>, c1/dec/d1<1>, c1/dec/d2<11>, c1/dec/d4<28>, ao<11>, c1/dec/d1<17>, c1/dec/d4<25>, c1/dec/d2<8>, ao<19>, cs<2>, c1/dec/d4<5>, c1/dec/d1<25>, ao<27>, c1/dec/d3<8>, cs<10>, m3<6>, cs<18>, c1/dec/d4<8>, c1/dec/d1<22>, c1/dec/d2<20>, m3<14>, cs<26>, m2<8>, m3<22>, c1/dec/d2<5>, m2<16>, m3<30>, c1/dec/d3<5>, N30, m2<24>, N26, c1/dec/d3<2>, m4<31>, c1/dec/d1<20>, c1/dec/d4<14>, c1/dec/d2<13>, ao<2>, c1/dec/d1<10>, c1/dec/d2<24>.
the code is
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rc5round is
port (
si : in std_logic_vector(32 downto 1); -- subkey
di : in std_logic_vector(64 downto 1); -- data in
do : out std_logic_vector(64 downto 1); -- data out
encdec :in std_logic;
data_in : in std_logic;
clk : in std_logic -- clk
);
end rc5round;
architecture Behavioral of rc5round is
component addsub
port ( a , b : in std_logic_vector (32 downto 1);
encdec : in std_logic;
c : out std_logic_vector (32 downto 1));
end component;
component circularshift
port (
sn : in std_logic_vector(5 downto 1);
di : in std_logic_vector(32 downto 1);
encdec : in std_logic ;
do : out std_logic_vector(32 downto 1)
);
end component;
component dff
port( d1 : in std_logic_vector (32 downto 1);
d2 : in std_logic_vector (32 downto 1);
data_in : in std_logic;
clk : in std_logic;
q : out std_logic_vector (32 downto 1)
);
end component;
component mux2b1
port ( d1 : in std_logic_vector (32 downto 1);
d2 : in std_logic_vector (32 downto 1);
encdec: in std_logic;
dout : out std_logic_vector (32 downto 1)
);
end component;
component xrgate
port ( a ,b : in std_logic_vector (32 downto 1);
c : out std_logic_vector (32 downto 1));
end component;
signal dr,dl : std_logic_vector(32 downto 1);
signal da,cs : std_logic_vector(32 downto 1);
signal m1,xo : std_logic_vector(32 downto 1);
signal m2,ao : std_logic_vector(32 downto 1);
signal m3,m4,db: std_logic_vector(32 downto 1);
begin
dl <= di(64 downto 33);
dr <= di(32 downto 1);
d1: dff port map ( m4, dr,data_in,clk, db );
d2: dff port map ( db,dl,data_in, clk, da );
mq1 : mux2b1 port map ( cs, da, encdec ,m1 );
mq2 : mux2b1 port map ( ao, xo, encdec ,m2 );
mq3 : mux2b1 port map ( da, cs,encdec ,m3 );
mq4 : mux2b1 port map ( xo, ao, encdec ,m4 );
x1 : xrgate port map ( db,m1,xo );
a1 : addsub port map (m3, si, encdec, ao);
c1 : circularshift port map (db(5 downto 1), m2, encdec, cs);
do <= da&db;
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
port( d1 : in std_logic_vector (32 downto 1);
d2 : in std_logic_vector (32 downto 1);
data_in : in std_logic;
clk : in std_logic;
q : out std_logic_vector (32 downto 1)
);
end dff;
architecture Behavioral of dff is
signal r : std_logic_vector (32 downto 1);
begin
process (data_in,clk,d1,d2)
begin
if data_in = '1' then
r<= d2;
else
r<= d1;
end if;
end process ;
process(clk,r)
begin
if (clk='1' and clk'event) then
q <= r;
end if;
end process;
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2b1 is
port ( d1 : in std_logic_vector (32 downto 1);
d2 : in std_logic_vector (32 downto 1);
encdec: in std_logic;
dout : out std_logic_vector (32 downto 1)
);
end mux2b1;
architecture Behavioral of mux2b1 is
begin
process (encdec,d1,d2) is begin
if encdec = '1' then
dout <= d1;
else
dout <= d2;
end if;
end process;
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xrgate is
port ( a ,b : in std_logic_vector (32 downto 1);
c : out std_logic_vector (32 downto 1));
end xrgate;
architecture Behavioral of xrgate is
begin
process ( a,b) is begin
c <= ( a XOR b );
end process;
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity circularshift is
Port (
sn : in STD_LOGIC_VECTOR (5 downto 1);
di : in STD_LOGIC_VECTOR (32 downto 1);
encdec : in std_logic;
do : out STD_LOGIC_VECTOR (32 downto 1)
);
end circularshift;
architecture Behavioral of circularshift is
component RC5ENCVROL
port (
sn : in std_logic_vector(5 downto 1); -- number of rotate steps
di : in std_logic_vector(32 downto 1); -- data in
doe : out std_logic_vector(32 downto 1) -- data out
);
end component;
COMPONENT RC5DECVROL
port (
sn : in std_logic_vector(5 downto 1); -- number of rotate steps
di : in std_logic_vector(32 downto 1); -- data in
dod : out std_logic_vector(32 downto 1) -- data out
);
end component;
component mux21
port (
doe : in std_logic_vector (32 downto 1);
dod : in std_logic_vector (32 downto 1);
encdec: in std_logic;
do : out std_logic_vector (32 downto 1)
);
end component;
signal doe,dod : std_logic_vector(32 downto 1);
begin
enc: RC5ENCVROL port map(sn , di ,doe);
dec: RC5DECVROL port map(sn , di ,dod);
m1: mux21 port map (doe , dod ,encdec , do);
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RC5ENCVROL is
port (
sn : in std_logic_vector(5 downto 1); -- number of rotate steps
di : in std_logic_vector(32 downto 1); -- data in
doe : out std_logic_vector(32 downto 1) -- data out
);
end entity;
architecture rtl of RC5ENCVROL is
signal d0 : std_logic_vector(32 downto 1);
signal d1 : std_logic_vector(32 downto 1);
signal d2 : std_logic_vector(32 downto 1);
signal d3 : std_logic_vector(32 downto 1);
signal d4 : std_logic_vector(32 downto 1);
signal r1 : std_logic_vector(32 downto 1);
signal r2 : std_logic_vector(32 downto 1);
signal r4 : std_logic_vector(32 downto 1);
signal r8 : std_logic_vector(32 downto 1);
signal d5 : std_logic_vector(32 downto 1);
signal r16 : std_logic_vector(32 downto 1);
begin
r1 <= d0(32-1 downto 1) & d0(32);
r2 <= d1(32-2 downto 1) & d1(32 downto 32-1);
r4 <= d2(32-4 downto 1) & d2(32 downto 32-3);
r8 <= d3(32-8 downto 1) & d3(32 downto 32-7);
r16 <= d4(32-16 downto 1) & d4(32 downto 32-15);
d0 <= di;
d1 <= r1 when (sn(1)='1') else d0;
d2 <= r2 when (sn(2)='1') else d1;
d3 <= r4 when (sn(3)='1') else d2;
d4 <= r8 when (sn(4)='1') else d3;
d5 <= r16 when (sn(5)='1') else d4;
doe <= d5;
end rtl;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RC5DECVROL is
port (
sn : in std_logic_vector(5 downto 1); -- number of rotate steps
di : in std_logic_vector(32 downto 1); -- data in
dod : out std_logic_vector(32 downto 1) -- data out
);
end entity;
architecture rtl of RC5DECVROL is
signal d0 : std_logic_vector(32 downto 1);
signal d1 : std_logic_vector(32 downto 1);
signal d2 : std_logic_vector(32 downto 1);
signal d3 : std_logic_vector(32 downto 1);
signal d4 : std_logic_vector(32 downto 1);
signal r1 : std_logic_vector(32 downto 1);
signal r2 : std_logic_vector(32 downto 1);
signal r4 : std_logic_vector(32 downto 1);
signal r8 : std_logic_vector(32 downto 1);
signal d5 : std_logic_vector(32 downto 1);
signal r16 : std_logic_vector(32 downto 1);
begin
r1 <= d0(1) & d0(32 downto 2 );
r2 <= d1(2 downto 1) & d1(32 downto 3);
r4 <= d2(4 downto 1) & d2(32 downto 5);
r8 <= d3(8 downto 1) & d3(32 downto 9);
r16 <= d4(16 downto 1) & d4(32 downto 17);
d0 <= di;
d1 <= r1 when (sn(1)='1') else d0;
d2 <= r2 when (sn(2)='1') else d1;
d3 <= r4 when (sn(3)='1') else d2;
d4 <= r8 when (sn(4)='1') else d3;
d5 <= r16 when (sn(5)='1') else d4;
dod <= d5;
end rtl;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux21 is
port (
doe : in std_logic_vector (32 downto 1);
dod : in std_logic_vector (32 downto 1);
encdec: in std_logic;
do : out std_logic_vector (32 downto 1));
end mux21;
architecture Behavioral of mux21 is
begin
process (encdec,doe,dod) is begin
if encdec = '1' then
do <= dod;
else if encdec = '0' then
do <= doe;
end if;
end if;
end process;
end Behavioral;