Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Finding positive flop to negative flop timing reports

Status
Not open for further replies.
K

kpsr

Member level 1
Joined
Mar 31, 2012
Messages
35
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,526
Hi folks,

I am doing synthesis (RTL compiler) it generate the different timing reports such as

input to output

input to seq

seq to seq

seq to output

But how to find the timing reports between positive flop to negative flop.

what are the commands are used for finding the timing between positive flop and negative flop

please give the solution as early as possible.

Thanks in advance
kpsr.
 

The timing between positive flop and negative flop is also categorized as seq to seq as well. Here the difference is, the data has only half clock period to meet setup instead of full clock period. But the advantage is gain of half cycle margin on hold check.
 
You can use "report_timing -from -to " to get specific path timing information.
 
  • Like
Reactions: kpsr

    K

    kpsr

    Points: 2
    Helpful Answer Positive Rating
in primetime when yu do report_timing you can see the report like this

Startpoint: ffa (rising edge-triggered flip-flop clocked by CLK)
Endpoint: ffd (rising edge-triggered flip-flop clocked by CLK)

now in the above case startpoint and end point is of both rising edge flipflop... and its because in the report_timing you have provided such paths with the help of -to and -from

so using these 2 switch you can change the reports.. apart of this there are few more switched like -rise_from -fall_from -rise_to and -fall_to .. use proper combination and validate it with the help of reporting header.
 
  • Like
Reactions: kpsr

    K

    kpsr

    Points: 2
    Helpful Answer Positive Rating
There are two types.

Positive and Negative edge triggered FF.
If Clock is driven by Positive edge triggered FF . Its Positive edge timing report.
If inverted clock driven by Positive edge triggered FF . Its negative edge timing report.

If Clock is driven by Negative edge triggered FF . Its negative edge timing report.
If inverted clock driven by negative edge triggered FF . Its positive edge timing report.

Now you got totally 4 combinations to analyze the reports.

if its single clock design, you can easily get this by writing simple perl script.
If its multi clock design, by using attributes, you can write simple script in PT/Dc.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top