Is 50 Celsius a normal temperature of a CPLD ?

CPLD too hot normal??

Hello,

I am using a MAX7000 CPLD. I enter a 20 MHz clock to a pin and output to another. The device gets 50º C (quite hot). Is this normal?.

Best regards,

mimoto

Re: CPLD too hot normal??

What exact device?

Look at the datasheet. There's a section called 'Power consumption'.

For example, an EPM7032, running at 20MHz, low-speed mode, 5V, room temperature have a typycal Icc current of 25mA.

P = I*V (ohm's law)... so...
P = 25mA * 5V
P = 125mW

Which is negligable power.

However, an EPM7256E, running 20MHz, high-speed mode, 5V, room temperature have typycal Icc current of about 375mA.

375mA * 5V = approx 1.9W. Which is enough to boost the chip of a few dozen degrees (if left without heat sink).

Note that this is typical power rating. With only a single clock in, and one signal out, this will be lower.

In other cases, look to make sure you don't have any pins set as output, shorting to something like VCC or GND.

Bottom line, it's all in the datasheets

One other thing that can really boost the power is leaving floating input pins. This have to do with the way MOSFET transistors work. Since the MOS inputs have really high impedance, leaving an input pin will make transistor oscillate, or randomly start and stop to conduct. Normally, the transistors act as a switch (either blocked or saturated). When blocked, no current run through it (so no power consumption). When saturated, maximum current flow through transistor, but negligable voltage difference between the transistor pins, so practically no power consumption either. But when the transistor is in mid-way, there is a zone where it have some current flowing though, with a voltage difference between the transistor pads. This will make the transistor dissipate power (as heat). This is also why increasing the frequency also increase device power consumptions, as a lot of transistors constantly switch between 'blocked' and 'saturated', and necessarely have to pass in this power-consumption zone at each transition (very brief, but the higher the frequency, the greater the time the transistor spend dissipating power). So, if you have floating input pins, look if you have an option to enable internal device pull-up resistors, for each input pins.

Re: CPLD too hot normal??

I think it may be caused by bus congestion. For instance, if two output are connected directly, there will be a large circuit through the pin

Re: CPLD too hot normal??

I had use MAX7064S with 40MHz clock the temperature rising (above environment) less than 15 degree.

CPLD too hot normal??

I think it is abnormal.
I have a design experience using max7128 and my design is reaching the 90% of the devece capacitance(both gates number and io pin number) and it works at a frequency of 25.175mhz.It does not more than 40º C after 2 hours runing at a room temperature of about 28º C