neocool
Member level 4
Hi,
I am using Xilinx ISE Webpack 6.2.03i.
I have updated my VHDL code and tried to update the testbench. It gives me an error, which says that it's unable to update the ports, .. check the syntax.. please see project navigator consolve for more details.
My code has passed the syntax test. I've tried to disable several ports, but still getting this error that prevents me from simulating my design.
Last time this occured when I was trying to use signed ports instead of std_logic_vector. What could be the potential problem now?
Here is the entity (types are defined in the package):
Thank you
I am using Xilinx ISE Webpack 6.2.03i.
I have updated my VHDL code and tried to update the testbench. It gives me an error, which says that it's unable to update the ports, .. check the syntax.. please see project navigator consolve for more details.
My code has passed the syntax test. I've tried to disable several ports, but still getting this error that prevents me from simulating my design.
Last time this occured when I was trying to use signed ports instead of std_logic_vector. What could be the potential problem now?
Here is the entity (types are defined in the package):
Code:
entity bpsk_mod_modified is
Port (
prtCLK: in std_logic; --40 MHz clock
prtBIT_CLK_IN: in std_logic;
prtDATA_IN : in std_logic;
prtCARRIER_IN : in sine_vector_type;
prtASYNC_RESET: in std_logic; prtBIT_CLK_OUT : out std_logic;
prtDATA_OUT : out bpsk_signal_type;
-- Test Points
tp_bit_counter: out std_logic_vector (8 downto 0);
tp_data_oversampled: out oversampled_signal_type
);
end;Thank you
