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vhdl programming using xilinx 7.1

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manasa4

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sir, I am doing a project on idea algorithm.during simulation ,it is showing a fatal error for the multiplication of two 16 bit inputs.is there any way to store the least significant 16 bits of the result in as 16 bit output from the 32 bits.should we use any library function.i m writing the code in vhdl and simultion using xilinx 7.1.here is the code for 1st round.


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity round1 is
    Port ( data : in std_logic_vector(63 downto 0);
           key : in std_logic_vector(127 downto 0);
           y : out std_logic_vector(63 downto 0));
end round1;
 
architecture Behavioral of round1 is  
signal x1,x2,x3,x4:std_logic_vector(15 downto 0);
signal z1,z2,z3,z4,z5,z6:std_logic_vector(15 downto 0);
signal p1,p2,p3,p4,p5,p6,p7,p8,p9,p10:std_logic_vector(15 downto 0);
signal y1,y2,y3,y4:std_logic_vector(15 downto 0);
 
begin
x1<=data(63 downto 48);
x2<=data(47 downto 32);
x3<=data(31 downto 16);
x4<=data(15 downto 0);
z1<=key(127 downto 112);
z2<=key(111 downto 96);
z3<=key(95 downto 80);
z4<=key(79 downto 64);
z5<=key(63 downto 48);
z6<=key(47 downto 32);
p1<=x1*z1;
p2<=x2+z2;
p3<=x3+z3;
p4<=x4*z4;
p5<=p1 xor p3;
p6<=p2 xor p4;
p7<=p5*z5;
p8<=p6+p7;
p9<=p8*z6;
p10<=p7+p9;
y1<=p1 xor p9;
y2<=p3 xor p9;
y3<=p2 xor p10;
y4<=p4 xor p10;
y<=y1&y2&y3&y4;
end Behavioral;

 
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remember, that 16 bit x 16 bit is a 32 bit result. To take the least significant 16 bits, use a temporary 32 bit signal, then assign off the LSBs.

Why are you using 7.1? thats very old - the latest version is 13.2 IIRC.
Finally - where is the clock? this design will not work very well without being synchronous.
 

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