Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to test for Dont care bits in VHDL test bench

Status
Not open for further replies.

hithesh123

Full Member level 6
Joined
Nov 21, 2009
Messages
324
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Location
lax
Activity points
3,548
Let's say I am testing a 16bit number, but only interested in the lower 8 bits.
How do I ignore the higher 8 bits.'
Is there a don't care(--) operation.
ASSERT my_data = X"--00" REPORT "ERR" SEVERITY ERROR;
This didn't work. Any other work around.
 

You have to remember that '-' (dont care) is an explicit state with std_logic, so unless that bit actually is '-', it will fail.
Like shan said, look at the lower 8 bits only ( using round braces, not square ).
 

Let's say I am testing a 16bit number, but only interested in the lower 8 bits.
How do I ignore the higher 8 bits.'
Is there a don't care(--) operation.
ASSERT my_data = X"--00" REPORT "ERR" SEVERITY ERROR;
This didn't work. Any other work around.

Use the std_match function from numeric_std!

ASSERT std_match(my_data, "--------00000000") REPORT "ERR" SEVERITY ERROR;
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top