Xilinx translate stage error "NGDBUILD 455" - multiple drivers

Hi i'm using Xilinx ISE 13.2 version. i'm generating the mig core and generating the clock through MMCM. the MMCM clock is further being connecte to the MIG. but i'm facing problems in translate stage. i'm getting these errors. My Synthesis is fine. kindly help.
:sad:
ERROR:NgdBuild:455 - logical net 'sys_clk_p' has multiple driver(s):
ERROR:NgdBuild:455 - logical net 'sys_clk_n' has multiple driver(s):
ERROR:NgdBuild:455 - logical net 'clk_ref_p' has multiple driver(s):
ERROR:NgdBuild:455 - logical net 'clk_ref_n' has multiple driver(s):
:sad:

you better post your code here

here s my code...

IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
) IBUFGDS_inst (
.O(CLKIN1), // Clock buffer output
.I(clk_p), // Diff_p clock buffer input
.IB(clk_n) // Diff_n clock buffer input
);

MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming ("HIGH","LOW","OPTIMIZED")
.CLKFBOUT_MULT_F(16.0), // Multiply value for all CLKOUT (5.0-64.0).
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (0.00-360.00).
.CLKIN1_PERIOD(5.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
// CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT1_DIVIDE(2),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
.CLKOUT4_CASCADE("FALSE"), // Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
.CLOCK_HOLD("FALSE"), // Hold VCO Frequency (TRUE/FALSE)
.DIVCLK_DIVIDE(8), // Master division value (1-80)
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
.STARTUP_WAIT("FALSE") // Not supported. Must be set to FALSE.
)
MMCM_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(), // 1-bit output: CLKOUT0 output
.CLKOUT0B(), // 1-bit output: Inverted CLKOUT0 output
.CLKOUT1(sys_clk_p), // 1-bit output: CLKOUT1 output
.CLKOUT1B(sys_clk_n), // 1-bit output: Inverted CLKOUT1 output
.CLKOUT2(clk_ref_p), // 1-bit output: CLKOUT2 output
.CLKOUT2B(clk_ref_n), // 1-bit output: Inverted CLKOUT2 output
.CLKOUT3(), // 1-bit output: CLKOUT3 output
.CLKOUT3B(), // 1-bit output: Inverted CLKOUT3 output
.CLKOUT4(), // 1-bit output: CLKOUT4 output
.CLKOUT5(), // 1-bit output: CLKOUT5 output
.CLKOUT6(), // 1-bit output: CLKOUT6 output
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock output
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT output
// Status Port: 1-bit (each) output: MMCM status ports
.LOCKED(LOCKED), // 1-bit output: LOCK output
// Clock Input: 1-bit (each) input: Clock input
.CLKIN1(CLKIN1),
// Control Ports: 1-bit (each) input: MMCM control ports
.PWRDWN(), // 1-bit input: Power-down input
.RST(RST), // 1-bit input: Reset input
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock input
);

BUFG BUFG_inst (
.O(CLKFBIN), // 1-bit output: Clock buffer output
.I(CLKFBOUT) // 1-bit input: Clock buffer input
);

The multiple_driver(s) problems are comes when we the signal is driven from two or more sources....

So here i think the signals sys_clk_p, sys_clk_n, sys_ref_p, sys_ref_n may be driven from two or more sources..

So better to check that first