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How does scaling voltage supply to lower levels reduces crosstalk?

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iVenky

iVenky

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I was learning "Digital Integrated Circuits" by Jan Rabaey where he states that one advantage of reducing the supply voltage to lower levels is that reduces the crosstalk.

I just couldn't understand how.

Could you please help me in sorting this out?

Thanks in advance.:grin:
 

allanvv said:
Smaller supply voltage means slower rise/fall times which means less crosstalk.
Click to expand...

I wouldn't think that smaller supply voltage necessarily means slower rise/fall times: LVDS drivers prove the opposite. And Fig. 4 of your a.m. paper states "Cross talk noise is a strong function of rise time and is a serious concern when rise time becomes less than 200 ps in deep-submicrometer technologies." -- which corresponds to lower supply voltage usage.
 

I also don't see a systematic relation between supply voltage and crosstalk. If you want to do increase rise- and fall-times arteficially, you can do easily, you don't need to modify the supply voltage for it.

I think, if the said author is claiming a relation, you should primarly try to follow his reasoning and possibly quote the key points here.
 

Perhaps rise time doesn't decrease but the dv/dt of the signals has to decrease since the transistors have smaller Vgs - Vth, and larger resistance. However the effect will be minor compared to performance loss from lowering VDD. I'm assuming the question means decreasing VDD for a specific process, not decreasing VDD through process scaling.
 

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