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[Verilog] Bitwise bidirectional port

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davorin

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Is there an elegant way to describe a bitwise bidirectional port in Verilog?

For example like in 8255/6522 chips where each individual bit can be configured as input/output?

I know that I can describe it bit by bit. But is there a more efficient way to describe it?
 

Depending on the FPGA, you may not necessarely have internal tri-state buffers required for doing so. However, each FPGA have tri-state IO.

The verilog keywork for a tri-state buffer is 'bufif0' and 'bufif1'. However, you may use specific verilog modules defined for your FPGA.

You simply have to put a connection from the pin input to the other pin's buffer input, in both directions, and control the gate as you wish. Make sure you don't enable both gates simultanously or else, undefined result may occur (either gates output will go to low or high, ingluding oscillation).

Code:
               Enable
       +------ B->A
       |
       |/|
       / |
    +-<  |----------------+
    |  \ |                |
A --+   \|          |\    +--- B
    |               | \   |
    +---------------|  >--+
                    | /
                    |/|
           Enable     |
           A->B ------+
 

module io(clk, port);
input clk;
inout [7:0]port;

reg [7:0]PortDir;
reg [7:0]OutData;

assign port[0] = PortDir[0] ? OutData[0] : 1bZ;
assign port[1] = PortDir[1] ? OutData[1] : 1bZ;

//this is not complete and just off the top of my head but that should give
//you the idea
 

assign port[0] = PortDir[0] ? OutData[0] : 1bZ;
assign port[1] = PortDir[1] ? OutData[1] : 1bZ;

I know that I can describe it bit by bit. But is there a more efficient way to describe it?

Please read my question first before answering...the question was if it can be done more efficient and scalable let's say for 64 bits or even more...
 

What description is the "more efficient method" which you consider to be an ideal?

I think it insufficient what your question expects the answer to.

I think that there is only a method which it generates 1 bit at a time using "for loop" syntax.
 

More efficient/scalable means:

That I don't have to write a seperate line for each bit (o;
This is okay for 8-bit ports...

But looks like there is no smaller construct in Verilog...
 

It can using "generate" syntax.
 

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