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sychronous circuits are provided with same clock and all the circuits work at each clock pulse synchronously.Whereas asynchronous circuits are provided with clock pulse for only first stage next stage depends on the o/p of first and so on.refer digital design by morris mano
Hi renoz
Two signals are said to be synchronous if they have certain timing relationship between them else we can say they are asynchronous..similarly in a design if output is sensitive of another signal(clock) then we can say that design is synchronous design. for example if you consider a fifo design in that if both read and write operations are depends upon a single clock then we can say that fifo is synchronous fifo, where as if we have different clocks for both read and write operations then it is said to be asynchronous fifo..hope you understand...
In verilog language this is how synchronous & asynchronous signals are being described. Assume we have reset and clock signals
// reset is synchronous with clock
always @ (posedge clock)
if (reset) // then reset the circuit
else // make the calculation with clock
// reset is asynchronous with clock
always @ (posedge clock or negedge reset)
if (reset == 1'b1) // then reset the circuit
else // make the calculation with clock
In the second example there is not any dependancy between reset and clock => reset and clock are asynchronous
In verilog language this is how synchronous & asynchronous signals are being described. Assume we have reset and clock signals
// reset is asynchronous with clock
always @ (posedge clock or negedge reset)
if (reset == 1'b1)
// then reset the circuit
else
// make the calculation with clock
In the second example there is not any dependancy between reset and clock => reset and clock are asynchronous
@haykp
in above i think the case you mentioned (@ negedge reset, if (reset == 1)) is never happens..
correct example is
always @(reset)
begin
if (reset == 1)
**reset the circuit**
else
**functionality**
for asynchronous with clock, you should not include the clock in always block
Regarding to including the clock in asynchronous logic, then have done this for explanation purposes, just to show the clear difference between sync and async designs.
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