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"Frequency Bridge" for data translation

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zorax85

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I'm working with two devices. One of them works at 50 MHz and the latter at 100MHz. Substancially from one side I should take data at 100MHz and translate them to 50MHz, and do the opposite on the other side. I should implement this bridge inside a CPLD, do you see any problem? Suggestions about how to make it working?
 

use a dual clocked FIFO. that would probably be the easiest approach.
 
TrickyDicky said:
use a dual clocked FIFO. that would probably be the easiest approach.
Click to expand...

Probably I'll follow that way, I have just used this approach last week in order to solve a similar problem. Thanks!

Other suggestions?

---------- Post added at 12:39 ---------- Previous post was at 11:41 ----------


Sorry, but as I told you before I'm using a CPLD, so it can not be possibile to use a core for a FIFO, that's why I was changing my approach instead of use the same of I already used (inside a FPGA).

XD
 

zorax85 said:
Sorry, but as I told you before I'm using a CPLD, so it can not be possibile to use a core for a FIFO
Click to expand...

the solution depends of specification,
[data are transferred randomly, as a bunch, size of bunch, can a sender
wait until receiver is ready etc.]

you can implement a simple handshake protocol
'sink50_ready_for_data, source100_data_valid, sink50_data_accepted',
'sink100_ready_for_data, source50_data_valid, sink100_data_accepted';

or you can emulate a simplified fifo with cpld registers;

---
 

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