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Will there be any phase difference between Clock input and its divided by 2 clock

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Hi,

I have a input clock running at 100 MHz. If I divide that clock by 2, then will there be any phase difference between input clock and divided by 2 clock (In this case 50 MHz) ...? I am using a D F/F to divide that clock.

Thanks
 

Yes, very much so. DO NOT divide clocks with FFs in logic, it causes lots and lots of problems in FPGAs.

If you use a PLL, you can garantee the two clocks are in phase, or any phase relationship you chose.
 

But I did not understand why there will be phase difference if I use Flip flops... I am not changing its phase part.. I am just dividing the frequency by 2.. May I know how will it affect the phase...

Thanks..
 

Perhaps you should clarify your understanding of the term phase difference first. TrickyDicky is obviously referring to the expectable time delay between active edge of the input clock and related divided clock edges.

In general signal theory terms, phase is ωt + Δφ, so (constant) phase differences can be only observed between signals of same frequency.
 

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