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questions about bias voltage, common mode voltage

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chaojixin

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when a large signal is applied to the input of S/H, the bias voltage and the common mode output voltage of diff-amp may be interfered and shows some fluctuation. increasing the decouple capacitance or bias current may reduce these fluctuation. but how can I ensure that the current or the capacitance is enough? should I keep these fluctuation under certain level? or only need to care about the differential output regardless of these common mode fluctuation?
any calculation method or simulation method?
the paper or other reference would be more I appreciated!

thanks in advance!
 

Are the fluctuations like spikes? Then more filter capacitor will help. Either across the supply rails, or from output to a supply rail.

Or else this problem may require a more stable voltage at the bias (meaning less resistance to your stable V reference),

or greater current capability from the supply,

or that you substitute a device that has less internal resistance at the output.

or that you add a buffer (voltage follower) after the output.

or that you increase resistance of your load connected to the output,.

Etc.
 

but how large cap/current is enough? overdesign is a waste of area or power
 

As an experiment try lower values of capacitor. See if the problem gets worse. This will tell you a lot.

I left out a question: Are you using an electrolytic for your S/H? I've seen them show jittery voltage fluctuations across the terminals. Possibly because it's old or leaky. Even when discharged, the internal chemistry can make a slight charge develop.

So consider using 2 or more capacitors in parallel to hold the charge. That might give more stability.
 

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