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Suggestion on circuit fabrication process

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srivatsan

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Fabrication

I dont know how many of you have actually fabricated a chip. I would be fabricating my analog devices by 0.5um technology, check www.mosis.org, AMC 0.5 runs. I would like to have some inputs regarding the precautions and necessary 'circuits' when fabricating. I am fabricating op-amps and few discrete devices and finally ADC in one chip. Let me know the possible problems that can be encountered. :?: :roll: thank you in advance........
 

Re: Fabrication

srivatsan said:
I dont know how many of you have actually fabricated a chip. I would be fabricating my analog devices by 0.5um technology, check www.mosis.org, AMC 0.5 runs. I would like to have some inputs regarding the precautions and necessary 'circuits' when fabricating. I am fabricating op-amps and few discrete devices and finally ADC in one chip. Let me know the possible problems that can be encountered. :?: :roll: thank you in advance........
Click to expand...

Watch out for temperature. Silicon in full-throttle operation can reach 125 degree C. Watch out for layer mapping, you do not want MOSIS to miss out a few layers on you, say M1 or Poly. Watch out for extraction rules, you do not want to miss some parasitic PN diodes, which can wreck havoc, or do inaccurate capacitance extractions.

I have done two TSMC 0.18um chips, with 10 modules on each, so I have had enough hard time with Cadence, MOSIS, NCSU CDK. Best luck!
 

Re: Fabrication

Thanks .. after a long time someone has actually fabricated something.

well, do MOSIS people provide any heat sink with the chip? beacuse my analog devices may let out good power dissipation. i will remember the temperature problem.

about the layers:if i follow their SCMOS Layout rules, then I think i should be in good position. if i have not got your point. please reply back. i will try to debug the parasitic PN diodes. if you have done that before, then get me an idea to start with. that will be helpful than the just quoting it.

also i am using cadence, and mosis; to do the analysis, i follow these steps: get the schematic and create netlist and take it and run it in spice with the actual model from MOSIS people. (it seems that for analog systems, it is better to get the models from the AMIS peolpe, but as you know they would not give because its IP). do you thnk it would have better probability of success?
since you have done before you know what works.... thats the reason the message is big.

relpy when you can.
thanks.
srivatsan
 

Re: Fabrication

DoctorX said:
Watch out for layer mapping, you do not want MOSIS to miss out a few layers on you, say M1 or Poly.
Click to expand...
DoctorX said:
Watch out for extraction rules, you do not want to miss some parasitic PN diodes, which can wreck havoc, or do inaccurate capacitance extractions.
Click to expand...
Those are exactly what I wanted to say.
I think SCMOS and your steps are good enough to have a successful chip. Actually the actual model is not guarantee if you don't simulate your circuits carefully. In addition, for ESD, if you don't have any special reason, the pad mosis provides is OK.
 

Re: Fabrication

Just in case, make sure for all inputs (CMOS gate, BJT Base) are properly connected. If unused, tie them to GND or Vdd/Vcc.

The divaDRC.rul coming with CDK is an attempt of one stone killing all, which is hard to achieve. It does not check:
(1) layer density rule, **broken link removed**
(2) wide metal rule: metals fatter than xxx um must have double spacing. TSMC said 10 um, MOSIS said 1 um. I use 2 um.

I modified those rule files are willing to share. Just ask.

In one word, be paranoid. Be paranoid at everything. One chip costs $25K+, you (and your supervisor) won't be happy if it screws up.
Will keep you posted if I think of anything.
 

Re: Fabrication

DoctorX said:
I modified those rule files are willing to share. Just ask.
Click to expand...
I'm more than willing to see that. Thanks!
 

Re: Fabrication

wide metal rule: metals fatter than xxx um must have double spacing. TSMC said 10 um, MOSIS said 1 um. I use 2 um.
Click to expand...

Regarding the 'wide metal rule' I suppose it is the one that demands extra spacing between gate and metal-layers if there are metal paths wider than 10um; It is still possible to use very wide metal paths in your design as long as you make slices in them (ie small openings/holes).
 

Re: Fabrication

Thanks to all of you.. please post all details whenever u wnat. i will be very happy to read it. if i encounter a problem,then i will post it immediately. also i would like to have the DRC rules, thanks DrX. i will most probably have atleast op-amp this week (testing with all parameter variations--> temp, DL or DW, Cox and all other process parameters.. just to be sure to anticipate what the heck will make my circuit go down the drain). thanks ...
srivats
 

Re: Fabrication

i have one more question: since my circuit would be drawing good amount of current, inorder to prevent the electromigration and other associated problems when a thin wire is carrying little heavy current, I need to have the width of the wire wider. how am i suppose to calculate the width for a given current? if you have done this befor let me know. thanks.
 

Re: Fabrication

srivatsan said:
i have one more question: since my circuit would be drawing good amount of current, inorder to prevent the electromigration and other associated problems when a thin wire is carrying little heavy current, I need to have the width of the wire wider. how am i suppose to calculate the width for a given current? if you have done this befor let me know. thanks.
Click to expand...

Rule of Thumb: 1 mA per 1 um width for 125-year lifespan (guaranteed for failure rate of ??). TSMC (confidential) docs have it.

Attached are the modified DRC and EXT rules. I cannot fully account what is inside, but it probably contains:
1. Wide metal separation rule;
2. Metal stress relief rule;
3. Exhaustive parasitic cap extraction rule;
4. Pay attention to anchor points marked with "Xiao", those are modified.

There is another thing that can send RF designs (and your fabbed chips) directly to TrashCo (C) or WasteManagement (C) depending on which one you contract: 3-side or 4-side extraction for Source/Drain diffusion capacitance perimeter, i.e., the Cjsw stuff. This difference is very, very bad for shared drain transistors and for RF designs, where parasitic caps are ruling Queens.

I know it 'cause it happened to me. Most books do not care to talk about it in detail, maybe the writers did not have hand-ons; and most RF engineers say that they do not know, either considering them as "trade secrets" or admitting it will bring back memories of bad experiences. Anyway, pay attention to it. If this is too vague, ask please.[/b]
 

Re: Fabrication

There is another thing that can send RF designs (and your fabbed chips) directly to TrashCo (C) or WasteManagement (C) depending on which one you contract: 3-side or 4-side extraction for Source/Drain diffusion capacitance perimeter, i.e., the Cjsw stuff. This difference is very, very bad for shared drain transistors and for RF designs, where parasitic caps are ruling Queens.

I know it 'cause it happened to me. Most books do not care to talk about it in detail, maybe the writers did not have hand-ons; and most RF engineers say that they do not know, either considering them as "trade secrets" or admitting it will bring back memories of bad experiences. Anyway, pay attention to it. If this is too vague, ask please.
Click to expand...

What do you mean ?, are the pex-tools extracting to few/many parasitics or is it the circuit models you are talking about ?
Please tell more details...
 

Re: Fabrication

Japp said:
There is another thing that can send RF designs (and your fabbed chips) directly to TrashCo (C) or WasteManagement (C) depending on which one you contract: 3-side or 4-side extraction for Source/Drain diffusion capacitance perimeter, i.e., the Cjsw stuff. This difference is very, very bad for shared drain transistors and for RF designs, where parasitic caps are ruling Queens.

I know it 'cause it happened to me. Most books do not care to talk about it in detail, maybe the writers did not have hand-ons; and most RF engineers say that they do not know, either considering them as "trade secrets" or admitting it will bring back memories of bad experiences. Anyway, pay attention to it. If this is too vague, ask please.
Click to expand...

What do you mean ?, are the pex-tools extracting to few/many parasitics or is it the circuit models you are talking about ?
Please tell more details...
Click to expand...

Assuming your FET has a drain diffusion width of a and length of b, where a is in a direction parallel to your gate. Most books (if they paid attention to this at all) say that the "drain perimeter" pd = a + 2*b, because of xxx reasons. Personally I think that in saturation region, because of channel pinch-off, the depletion region near the drain facing the channel is much wider than other part surrounding the drain, so it is ignored.

Anyway, if you do a+2*b, you will underestimate your Cjsw*pd and underestimate your Cjd. If you use interdigitated FETs, the pd = 2*b because the diffusion facing two gates and the 2 a's are ignored. This is disaster, at least for designs sensitive to parasitic capacitors. Unfortunately, CDK by default does this, and most books say so. Even Thomas Lee forgot to mention this in his book.

The correct way is to use 2*a + 2*b for RF designs, which tend to over-estimate your Cjd, if this is ok with you.
 

Re: Fabrication

Yes, pay attention to "XPART"'s value in your SPICE models. Xpart tells the simulator how to distribute channel charge between source and drain. Most models use 0, which means that it is 100% assigned to source, which tend to under-estimate Cdd, the drain capacitance. Xpart = 0.5 do even partition.

How to deal with it depends on your specific situation.
 

Re: Fabrication

i need to know about the ESD protection that is provided by the MOSIS people. also i see that they fabricate with clean environment but what about ESD circuits inside the chip? do they add it like default or is it upto me to get a circuit for that?
anyone who has fabricated .. plz answer.. thanks in advance..
srivatsan
 

Re: Fabrication

srivatsan said:
i need to know about the ESD protection that is provided by the MOSIS people. also i see that they fabricate with clean environment but what about ESD circuits inside the chip? do they add it like default or is it upto me to get a circuit for that?
anyone who has fabricated .. plz answer.. thanks in advance..
srivatsan
Click to expand...

For ESD circuitry, you have to fend for yourself. If you are lucky enough to get the Tanner (or Taner??) PAD libraries before the run deadline, they have included some ESD for you. I was not lucky enough, so I did a full-customized design of PADs, with their ESD part. The ESD on my PADs is overkill, but I am not worried, as the pads are only used for low-frequency biasing.
 

Re: Fabrication

I really dont know the Tanner PADs. What are they..

also where to start for ESD pads? let me know. thanks DrX.
srivatsan
 

Re: Fabrication

Hi guys,
My fabricated chip worked prefectly. I am awaiting ADC and DAC.. let me see what happens then..
I thank all guys who had a say in fab process...
Regards,
Srivats
 

Fabrication

i am doing someing about adc,this article is useful to me,thx guys!
 

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