Re: delay code in vhdl

Re: delay code in vhdl

Hi, I have an LED connected to CPLD I/O port i wrote the vhdl code to toggle the LED, but it is not visible. can anyone help me how to write a delay in vhdl with an example so that LED blinking is visible outside. do i need to use any looping technique. please help me:sad. Advance thanks.

I wrote the program like (only architecture part)


architecture Behavioral of toggle is

begin

c<=not c after 3000ms;


end Behavioral;

Re: delay code in vhdl

Delay statements are simulation tools and don't work for hardware synthesis. You should consult your VHDL text book about the point. You'll need a clock connected to the CPLD, e.g. a crystal oscillator. You can divide it down to any low frequency you need.

Re: delay code in vhdl

oh okay... can we do it using counter in the programming.???

Re: delay code in vhdl

Yes Please use counter based on the delay requirement.It will work

Re: delay code in vhdl

can we do it using counter in the programming.???

Click to expand...

That's another word for dividing frequencies in my view.

Re: delay code in vhdl

FvM said:

That's another word for dividing frequencies in my view.

Click to expand...

Yes it is........................

Re: delay code in vhdl

thank you sivamani and FvM... I wrote the code like (only architecture part)

architecture Behavioral of ctr is

begin
process(clk)
variable cnt:integer:=0;
begin
loop
--wait until clk='1';
cnt:=(cnt+1) mod 65535;
if(cnt=65535)then
c<=cnt;
end if;
end loop;
end process;

end Behavioral;



It is showing the error like

ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.

how to resolve this..

Re: delay code in vhdl

your process is unclocked. you must clock the processs

Re: delay code in vhdl

karthiks30 said:

thank you sivamani and FvM... I wrote the code like (only architecture part)

architecture Behavioral of ctr is

begin
process(clk)
variable cnt:integer:=0;
begin
loop
--wait until clk='1';
cnt:=(cnt+1) mod 65535;
if(cnt=65535)then
c<=cnt;
end if;
end loop;
end process;

end Behavioral;



It is showing the error like

ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.

how to resolve this..

Click to expand...

Why cant you write code in this way?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity LED is

port
(
D : out std_logic_vector (3 downto 0);
clk_50MHz : in std_logic;
reset_n : in std_logic
);

end entity;

Architecture behaveior of LED is

signal count :std_logic_vector(19 downto 0);
signal Data :std_logic_vector (3 downto 0);
Signal rst_low :std_logic <= "0";

begin

Process(clk_50MHz)

if rising_edge(clk_50MHz) then
if (reset_n = rst_low) then
count <= (others => '0');
data <= "0000";

else
count <= count + '1';
if(count = 0) then
data <= data(0) & data(3 downto 1);
end if;
end if;
end if;
end Process;

D <= data;

end behaveior;

---------- Post added at 05:31 ---------- Previous post was at 05:30 ----------

sivamani said:

Why cant you write code in this way?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity LED is

port
(
D : out std_logic_vector (3 downto 0);
clk_50MHz : in std_logic;
reset_n : in std_logic
);

end entity;

Architecture behaveior of LED is

signal count :std_logic_vector(19 downto 0);
signal Data :std_logic_vector (3 downto 0);
Signal rst_low :std_logic <= "0";

begin

Process(clk_50MHz)

if rising_edge(clk_50MHz) then
if (reset_n = rst_low) then
count <= (others => '0');
data <= "0000";

else
count <= count + '1';
if(count = 0) then
data <= data(0) & data(3 downto 1);
end if;
end if;
end if;
end Process;

D <= data;

end behaveior;

Click to expand...

this code for roling leds with around 300ms time

Re: delay code in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
port(C : in std_logic;
Q : out std_logic:='1');

end counter;

architecture archi of counter is
signal t: std_logic:='1';
constant cnt_max :natural := 250000000;
begin

process (C)
variable cnt : natural range 0 to cnt_max :=0;
begin
if (C'event and C='1') then
cnt := cnt + 1;
if(cnt=cnt_max)then
t<= not t;
cnt:=0;
end if;
end if;
end process;
Q<=t;
end archi;


I have a JTAG connected to cpld.. clk pin is connected to I/OGCK and Q is connected to blink the LED. But still the LED is not toggling.. Do I need to provide any external crystal oscillator to the GCK pins of the cpld?? please help me.. thank you in advance..

Re: delay code in vhdl

Do I need to provide any external crystal oscillator to the GCK pins of the cpld??

Click to expand...

As discussed before in this thread.

Re: delay code in vhdl

Thank you for helping me out guys.. it worked, I connected the external clock for clk.....