Doubts in ASIC frontend flow

i've some doubts..please give me the solutions

1) what is main difference between simulation and verification??both using for checking design functionality, then why we done those both differently??
2) what is corner case??is every case in test vectors is corner case??
3) is functions are used in verification??
4) what is race around problem??
5) what is exact definition of high impedance?
6) Actually we getting all the timing information from libraries na..then why we are again specifying those in constraint file??
7) what is design architecture exact work??
8) where the DFT exactly performed??i mean at which level??

1- simulation is one way to check a functionnality. But the functionality could be check, with code review, equivalent checking...
2- in simulation, corner case, mean, for example for a clock divider, simulate min, max and some values. When you have asynchronous clocks, try the worst combination (ratio)
3-??
4-It is mainly due to hardware, when one external wire could "run" faster than an other one.
5-
6- constraints files indicates what the design frequency should reach (for ex.), the library does not know, what you want to do with your design.
7- find the best architecture to feet your requirement, in term of frequency/power/area....
8- in general, the DFT occurs during the synthesis phase.

just some add up.
1) Simulation is one way of verification and there are other ways to verify a design, such as LVS, formal verification, etc.
2) Corner case can have many meanings. In functional verification, corner case can be the test cases which is not covered by general test cases. In Synthesis, corner has a special meaning of different working environment. For the normally used three corners situation: fast corner (high supply voltage, low temperature), normal corner (normal supply voltage, 25 C), worst corner (low supply voltage, high temperature)
5) High impedance normally means large resistance which constrain current to a very low volume.
6) Timing info in cell libraries are use to calculate the delay of certain circuit. The constraints represent the delay we want the circuit to be. By change to structure of certain circuit without affect its function, we may get faster circuit which meet the constraints. This is what the optimization do in synthesis.
7) DFT, design-for-test. Normally means insert scan chains to RTL circuits. Insert clock gate to generate slow clock for scan chains which can be used when test the chip. BIST to test the function of memory components. And some time other test circuit for special circuits. These test function can be added in design, such as the clock gate, test control pins, or special test circuits. Scan chains are most likely to be inserted automatically by the synthesizer.

thanks for giving the valuable information...

if dft is performed at synthesis level then how can we find the manufacturel defects?

---------- Post added at 11:39 ---------- Previous post was at 11:31 ----------

i already completed PG diploma six months training in ASIC frontend flow..i passed in 2011..is there any chances to get job in VLSI logic design..if there...please tell me

the ATPG tool read model of std-cell/memories... faults, and generate the patterns on the DFT material (scan chain... test points...) to check the consistency of the silicium.

in synthesis, as a part of specifying timing exceptions constraints, how can we find the "false paths" to set as constraint...
eg: set_false_path "-from U1 -to DATA1"
in above example how can we know that path from U! to DATA1 is the false path..

please give me tha clarification

The "mandatory" constraints are frequency system & I/O constraints to check the timing versus the "world".
The false path are not required if you reach the timing in the area/power budgets. You could add false path to simplify the constraints.
So by default the sdc could very simple.