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Combinational or Sequential? A question about "Process&

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Victory1981

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A Process statement can be synthesised into combinational circuit and sequential circuit. Is there any general rule to determine which kind of circuit it will be synthesised into?

An example:

p1:process(Clock)
Begin
If rising_edge(Clock) then
Case State Is
When S0=>
If XXXX then
State<=S1;
End If;
When S1=>
If XXXX then
State<=S2;
End If;
...
End Case;
End If;
End;

p2:process(State)
Begin
Case (State)
When S0=>
Output<=XXX;
When S1=>
Output<=XXX;
...
End Case;
End Process;

p1 was synthesised into sequential circuit while p2 was combination circuit.
Why? Is there any general rule?

Thank you.
 

Re: Combinational or Sequential? A question about "Proc

In the first process you will find :

1- IF statment
2- Clock

I think Both of them can make this difference
 

Re: Combinational or Sequential? A question about "Proc

Because the first one has the clock information and the second one does not.
 

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