Tools For ASIC/FPGA Verification Engineer

What programming languages are important to know to get a job in Verification Engineering field? I know Verilog and SystemVerilog are 2 of the most important languages. What other languages are frequently used by verification engineers, in order of priority?

Perl (OMG you need to know perl)
C/C++ (DPI/VPI and the sorts for comparing against algo)
Tcl (b/c of the tools)
SystemC (possibly)
Matlab (if you do DSP work)

for verification methodology you should be familiar with OVM/UVM/VMM!

Hi

If you want to become Verification Engineer...First you should perfect in below concepts

Digital Design, Verilog, System Verilog, C++...
Scripting Languages(PERL/Tcl)...

Search in google ASIC Logic design..you will come to know about all...
please once check below site

https://www.cs.umbc.edu/~cpatel2/links/641/slides/lect01_flow.pdf

just a summary of all the post above.
For verification, the most relevant languages are:
Verilog/VHDL (the implementation or the language for DUT)
SystemC, SystemVerilog, Vera, e language (these for test benches)

Of course, following languages are also important:
C/C++ (C++ is the basis of SystemC, and C/C++ is the major coding language for VPI)
PLI/DPI/VPI are the programmable interfaces, they are extreme useful when the simulator cannot directly support SystemC/SystemVerilog or some special functions are needed. But in normal cases, you dont need to produce PLI/DPI/VPI from scratch as they are provided.
Perl/Tcl/Bash/Lisp these are script language. They are extremely useful when you want to automise your verification whichout human interaction. From a strict point of view, they are not directly relevent to verification as they are usually required by all EDA tool flow.
Matlab/SPW These are high-level prototype tools used by architects. It is desirable for verification engineers to understand them but not essential.

Something about concepts:
OVM/UVM/VMM these are verification methodologies rather than languages. It is quite important for good verification engineers to follow them.

SystemVerilog, SystemC and OVM ( Open Verification Methodology ), C/C++, Verilog, Perl , Unix/Linux tools are all pretty good. For some excellent Verification Engineer career descriptions take a look here --> Online Jobs

can anyone know about specman tool? Does this tool use for verification and is it freely available for students?

Do you mean the Verisity Specman tool suite using e language?
It is a tool for functional verification.
Verisity is bought by Cadence now and Specman is a part of Cadence tools.
It is not free. If your University have Cadence support, you can ask for the tool from Cadence through your university.

can anyone please tell me the difference between verilog and system verilog language?? and among system verilog and vhdl, which one is the more advanced one?

Verilog language can be used to create synthesizable RTL and can be used also in simulation,System Verilog mainly used to verify the design .

System Verilog is OOP based language based on classes but Verilog based on modules.

Mainly if you want to design something you can use Verilog or VHDL and if you want to verify that design and see if it works properly as expected to be you will use System Verilog.