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compiling a protected verilog file (*.vp)

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muni123

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Hi,

What is the command to compile a protected verilog file in NC-sim. what are the options we need to consider before compiling a protected verilog file (*.vp file)

ref:
https://www.edaboard.com/threads/7269/

Thanks in advance!!!
 

with respect to vcs:
provide the switch : +libext+.vp in the vcs compilation command; rest the vcs tool will take care of it.
 

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