metalnumb
Newbie level 4
Hey Guys ! i'm writing a VHDL Code to describe a serial in parallel out shift register -which is not that hard- but the problem is the constraints that's imposed on me by the required project:
its required that if the first bit of the sequence is 1 then the register will begin to recieve data serially, but the problem is i cant do it in VHDL unless i want the register to actually RESET everytime the first bit is a 0,which is wrong... anyways here's my code.....appreciating any help and sorry for the LONG post :/
its required that if the first bit of the sequence is 1 then the register will begin to recieve data serially, but the problem is i cant do it in VHDL unless i want the register to actually RESET everytime the first bit is a 0,which is wrong... anyways here's my code.....appreciating any help and sorry for the LONG post :/
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 entity REG is Port ( din : in STD_LOGIC; clk : in STD_LOGIC; data : out STD_LOGIC_VECTOR (6 downto 0); data_valid : out STD_LOGIC; err : out STD_LOGIC); end REG; architecture Behavioral of REG is begin process(clk) variable tmp:std_logic_vector(9 downto 0); -- it's a variable because i need it to change value variable parity:std_logic; -- instantaneously for other project requirements :/ begin if (tmp(9)='0') then tmp :=(others=>'0'); elsif(clk'event and clk='1')then --if first bit of the sequence=1,at the +ve edge.. tmp := din & tmp(9 downto 1) ; -- the register begin to recieve input serially end if;