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declare verilog ports in VHDL testbench

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yuanqi

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Hi.
I declare an array port in VHDL which is "IS ARRAY (8 DOWNTO 0) OF std_logic_vector(1 DOWNTO 0)". After synthesis, this port is flatten into "input [1:0] \data_in[0] , \data_in[1] , \data_in[2] , \data_in[3] , \data_in[4] , \data_in[5] , \data_in[6] , \data_in[7] , \data_in[8] ;" in Verilog.
The problem is when I want to instantiate this module in my VHDL testbench, the simulator cannot find the port "data_in" in the synthesized module any more. What should I do now? Thanks a lot!
 

Looks like you shouldn't use 2-D arrays in your VHDL top entity, if you wnat to simulate it. I guess, the problem will only only occur in a simulation of sub-entities, because it's very unusual to have 2-D ports in the design top.

You can write a simple wrapper that flattens the 2-D port to 1-D and instantiate it as design top for simulation.
 

right now, I find the problem is the change of the name from "data_in" to "\data_in", but in vhdl I cannot declare any signal or ports with names starting with backslash. Is there any way to create such kinds of name?
 

Is there any way to create such kinds of name?
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No. Actually, I don't understand how the problem is brought up. Normally, simulating a post-synthesis netlist doesn't require any manual action, it's smoothly performed by the simulator tool. That's why I guessed that the issue has been caused by an unsuitable top level port type.
 

I found all the 2-D signals are flatten by the synthesis tool(RTL complier), and with one additional backslash at the beginning. Let me try to avoid 2-D port at the lop level entity. Thanks a lot!
 

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