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Looking for Layout/Design Guidelines on PLL in 90nm process.

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kamchor

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I am new to PLL design and so I am looking for some guidelines both in
design and layout mostly related to 90nm process.

Any suggestions on
current density estimation
metal density estimation
decoupling capacitor estimation for Analog VCC and Digital VCC.
decoupling capacitor estimation between Quite VCC and VSS.

Any other suggestion or link to any papers is welcome.
 

Re: Looking for Layout/Design Guidelines on PLL in 90nm proc

Hmmm, you are new to PLL design and require assistance in 90nm layout.

You should know that 80% chips fail first silicon. Article link below.

You can try (for other articles)

circuitsage.com

Also try aicdesign.org and Professor P.E. Allen's website for his synthesizer course notes.


There would be no mention of a 90nm process in the above, since this is fairly new technology and there are not many publications about it either. You can discuss with your company colleagues.

----
**broken link removed**

----- EXCELLENT ARTICLE ON 90nm ISSUES

**broken link removed**

----

Best of Luck.
 
Re: Looking for Layout/Design Guidelines on PLL in 90nm proc

Hi

Could someone explain more on the 90nm technology/technology files and design chalanges?




tnx
 

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