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Help me make a clock divider in VHDL using Altera FPGA

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aeneas81

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clock divider

Dear all,
I would to write a PLL kind of stuff using VHDL using @ltera fpga, and would sincerely appreciate any ideas on doing it. I'm trying to derive a 12MHz clock from a 48Mhz clock. The 12MHz clock will only start generating once a predefined input sequence pattern has been receive. The input is also 12MHz based.
I've try to use din'EVENT to detect changes in input signal, but the din'EVENT is true only when din changed from 0 to 1, or when din stay in 1. What i want is to be able to detect either from 0 to 1, or from 1 to 0.
It's kind of complicated in my explanation, but still hope you'll get my point here.
Thanks a lot in advance!
 

Re: clock divider

To detect a 0->1 or 1->0 transition use a flip-flop to store the CurrentSignal. Then compare CurrentSignal with OldSignal (the previous signal).

If NOT(CurrentSignal) AND OldSignal = 1 then a 0->1 transition occured, similiar for the 1->0 transition.

To generate the 12MHz clock use a divider by 4 (2 flip-flops) sourced by the 48MHz clock. If the divider value is 3 (q0 AND q1) generate an output signal.

If you give this divider a clock enable you can control output clock generation.
 

Re: clock divider

Yes. Simple detect circuit is flip-flop with xor gate.
for example:

process(clk_i)
begin
if rising_edge(clk_i) then
q <= d;
end if;
end process;

change_state <= d xor q;

but this example is not glich free...
For more examples see sources of project usb_phy at www.opencores.org
 

Re: clock divider

for clock dividing either u can use shift register of u can use counters. in xilinx ISE u have clk PLL where there is one divider output where u can use ur correct to get the desired output.


ashish
 

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