aeneas81
Junior Member level 1
clock divider
Dear all,
I would to write a PLL kind of stuff using VHDL using @ltera fpga, and would sincerely appreciate any ideas on doing it. I'm trying to derive a 12MHz clock from a 48Mhz clock. The 12MHz clock will only start generating once a predefined input sequence pattern has been receive. The input is also 12MHz based.
I've try to use din'EVENT to detect changes in input signal, but the din'EVENT is true only when din changed from 0 to 1, or when din stay in 1. What i want is to be able to detect either from 0 to 1, or from 1 to 0.
It's kind of complicated in my explanation, but still hope you'll get my point here.
Thanks a lot in advance!
Dear all,
I would to write a PLL kind of stuff using VHDL using @ltera fpga, and would sincerely appreciate any ideas on doing it. I'm trying to derive a 12MHz clock from a 48Mhz clock. The 12MHz clock will only start generating once a predefined input sequence pattern has been receive. The input is also 12MHz based.
I've try to use din'EVENT to detect changes in input signal, but the din'EVENT is true only when din changed from 0 to 1, or when din stay in 1. What i want is to be able to detect either from 0 to 1, or from 1 to 0.
It's kind of complicated in my explanation, but still hope you'll get my point here.
Thanks a lot in advance!