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How can I reduce the drop out voltage in LDO ?

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santhoshv78

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ldo with depletion nmos

How can I reduce the drop out voltage in LDO..
Is it only by increasing the size of power transistor.
Thanks
 

ldo thesis gabriel alfonso

add (or reduce for pmos) the gate voltage
or change the well voltage, but be careful of the pn junction
 

drop out voltage in LDO

for a standard LDO - yes, a bigger mosfet is the only way to reduce dropout.

some advanced methods are to:
-use low-threshold or depletion device as pass transistor
-body boost (modulate the tank voltage in order to make body effect lower Vt)
-charge pump the gate higher than Vin.
 

Re: drop out voltage in LDO

use a ext mosfet to reduce voltage drop,more smaller RDS will get more lower voltage drop.
 

Re: drop out voltage in LDO

another Use DMOS
 

Re: drop out voltage in LDO

I am using PMOS native pass transistor. The RDS required is arround 1.2ohms. I canot increase the size too much since the transient gives more overshoot in the settling behaviour than the specification.(phase margin problem?)..I am using a simple differential stage as the error amplifier. First pole is at the output of error amplifier and second pole at the LDO output. Load capacitor is 4.7uF with 1ohm ESR resistor.

Will u give more information abt DMOS also..
 

drop out voltage in LDO

The phase margin problems probably come from the fact that you are using a miller opamp for the error amp.

When you increase the PMOS, you increase the capacitive load seen by the opamp. Driving a bigger cap needs more miller-compensation. All you need to do to drive a bigger cap (pass device) is to increase the compensation.

In order to do this efficiently, you should use a resistor in series with your compensation cap. This adds a zero that cancels out the zero of the drive transistor. The resistor value should be about 3x the gm of your drive transistor (output fet of opamp, not pass device) Usally 2k-10k is where I end up putting them, in series with the comp cap. Now your comp cap is much smaller for the same phase margin.

Another idea would be to use a folded cascode error amp instead of miller amp. Now your main pole is at C*Rout of the cascode amp. Driving a bigger cap makes you MORE stable. That would be my choice for your project.

DMOS is very powerful for it's size, so therefore very efficient. Better in my opinion for switching applications than for linear apps. Maybe a lateral DMOS would be good because you don't need to use the substrate, but most vertical DMOS I've seen use the substrate, which you don't want connected to the outside world, except to GND..

I think PMOS is a good choice for you. Gabriel Alfonso Rincon Mora wrote his thesis on LDO's, I think you will get a lot of ideas from it. He also talks about body boosting, which for a PMOS means drawing a tiny amount of current out of the body. Vt is lowered and the output fet seems more powerful. I have only seen one successful implemenation of this so I urge you to stay away until you get the standard implemenation working well. Drawing ANY current out of the body puts you at high risk for latchup, which is really bad when a 1A mosfet latches up.

My suggestion is to increase the PMOS to 1.2mOhm at your lowest dropout spec. Now increase the compensation on the miller amp until it is stable at cold temp, fast models. Or, switch your error amp to a folded cascode, and the big cap (PMOS gate) should give you a pretty stable system.
 

Re: drop out voltage in LDO

dear electronrancher,
can u plz post thesis of Gabriel Alfonso Rincon Mora..I am not able o get it from other sources..
regards
 

drop out voltage in LDO

Hi,electronrancher

I am wondering your fold_cascode structure's stablity. Because there are two pole at low frequency: one is formed by the output cap and output resistor, the other formed by the big mos's gate capacitance and the output resistor of the amplier.

How can you make sure your systme is stable?And
which pole is the dominant pole?How about the Zero formed by ESR and output cap?
 

Re: drop out voltage in LDO

electronrancher said:
The phase margin problems probably come from the fact that you are using a miller opamp for the error amp.

When you increase the PMOS, you increase the capacitive load seen by the opamp. Driving a bigger cap needs more miller-compensation. All you need to do to drive a bigger cap (pass device) is to increase the compensation.

In order to do this efficiently, you should use a resistor in series with your compensation cap. This adds a zero that cancels out the zero of the drive transistor. The resistor value should be about 3x the gm of your drive transistor (output fet of opamp, not pass device) Usally 2k-10k is where I end up putting them, in series with the comp cap. Now your comp cap is much smaller for the same phase margin.

Another idea would be to use a folded cascode error amp instead of miller amp. Now your main pole is at C*Rout of the cascode amp. Driving a bigger cap makes you MORE stable. That would be my choice for your project.

DMOS is very powerful for it's size, so therefore very efficient. Better in my opinion for switching applications than for linear apps. Maybe a lateral DMOS would be good because you don't need to use the substrate, but most vertical DMOS I've seen use the substrate, which you don't want connected to the outside world, except to GND..

I think PMOS is a good choice for you. Gabriel Alfonso Rincon Mora wrote his thesis on LDO's, I think you will get a lot of ideas from it. He also talks about body boosting, which for a PMOS means drawing a tiny amount of current out of the body. Vt is lowered and the output fet seems more powerful. I have only seen one successful implemenation of this so I urge you to stay away until you get the standard implemenation working well. Drawing ANY current out of the body puts you at high risk for latchup, which is really bad when a 1A mosfet latches up.

My suggestion is to increase the PMOS to 1.2mOhm at your lowest dropout spec. Now increase the compensation on the miller amp until it is stable at cold temp, fast models. Or, switch your error amp to a folded cascode, and the big cap (PMOS gate) should give you a pretty stable system.
Click to expand...
I am puzzled here for the miller compensation and cascode output structure for a traditional LDO with a large C connect to the output.
can anyone give me a link of a papar about the miller compensation ldo?
 

Re: drop out voltage in LDO

Here is the link to the LDO thesis:

Current Efficient, Low Voltage, Low Dropout Regulators
by Gabriel A. Rincón-Mora
Ph.D. Thesis in G. I. T. 1996
Volume: 198 pages

**broken link removed**
 

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