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who can tell me the differences between two foundry for the same 0.5um CMOS process!

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for example, I Have one IP which is designed based on the TSMC 0.5um CMOS process, and now i want to design new chip which would be taped out at Charted, So i wander the process gap between them, who can tell me ? just a tiny difference ?
 

As you said a little bit and I saw a little difference in passive component.(pirting from tsmc to st 65nm)
 

Thank you, Milad, if I WON'T modify the tsmc cmos 0.5 um based Design, just do layout verificaiton(drc). and then tapa out this disign at Charted, can anyone evaluate the chip performance?
 

There will be differences in DRC rules mostly minor. Much more important would be differences in required tapeout layers, logic operations and stream maps:
e.g. in TSMC the presence of certain layers completely suppresses the automatic generation of associated layers
TSMC usually requires tapeout of of both n and p implants while IBM derives n implants
...

Very easy to get a useless piece of silicon back. Even changing PDK or design house for the same foundry is sufficient to mess up completely your tapeout.
 

Better you check the layer mapping before you go ahead with tape out..and the rule set may be different..It is not advisable to go ahead with your plan without thorough verification.
 

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