starsunmoon
Junior Member level 1
Hello everyone,
After passing DRC/LVS, I did a parasitic-extracted calibre-view simulation on a top level analog circuit block, and results were mostly off : a few sub blocks were correct but most sub blocks gave weird values (a couple hundred millivolts near power rails). However, switching back to schematic simulation still gave correct results.
So instead of using a top calibre view for the top level block, I kept the top block in the schematic view and converted all its sub blocks into calibre views one-by-one. Re-simulated, and results were as correct as schematic simulations.
Even weird, I generated a top calibre view again for the top level block, except this time with parasitic switches off (so no parasitic was generated). Then re-simulate the parasitic-free top-level calibre view, and results were as wrong as my previous top calibre view results with parasitics.
Wondering if someone knows any reason or suggestions.
Very appreciated !
After passing DRC/LVS, I did a parasitic-extracted calibre-view simulation on a top level analog circuit block, and results were mostly off : a few sub blocks were correct but most sub blocks gave weird values (a couple hundred millivolts near power rails). However, switching back to schematic simulation still gave correct results.
So instead of using a top calibre view for the top level block, I kept the top block in the schematic view and converted all its sub blocks into calibre views one-by-one. Re-simulated, and results were as correct as schematic simulations.
Even weird, I generated a top calibre view again for the top level block, except this time with parasitic switches off (so no parasitic was generated). Then re-simulate the parasitic-free top-level calibre view, and results were as wrong as my previous top calibre view results with parasitics.
Wondering if someone knows any reason or suggestions.
Very appreciated !