scripts in simulating with Modelsim or Active HDL

Does somebody can provide a good tutorial or example for using scripting when simulating with ModelSim?

Thanks

lucbra,

I have used Modelsim for a long time, 10+ years, and I use/published this package:
The VHDL Test Bench :: Overview :: OpenCores

It is a fully documented scripting system written in VHDL. It enables the user to create thier own scripting language for directing and checking simulations. I have used this system for many FPGA & ASIC designs. I also use tcl/tk to generate the scripts for me, when I want to randomize or automate some of the testing.

Hope that helps.

Sckoarn

If you are writing a testbench for any simulator you should try to make a general interface that can be reused and read in the test data externally. General interfaces with {data, req, ack} signals work well. This interface should be a vhdl or verilog wrapper so that you can instantiate your test core.

You should read your test data from a file that can easily be changes independently from the wrapper. You can then reuse your wrapper code easily as well as swap your test data quickly. You can generate your test data using any other language - python and perl are a good idea. You can then make a tcl "run" script that generates your test data, compiles your design and wrapper, starts the simulation and adds the ncessary signals to the wave form.

For help managing and checking test infrastructure you might like to try our tool called Breeze. Breeze traces your flow so you can see which files and be used, where your report files are going and you can access your scripts. When you are done you can document the flow automatically so that you can reuse it another time. It is based on eclipse, but is able to understand systems with many tools and many programs. It is not a substitute for good working practices such as the VHDL testbench, but it helps you to make sure you have got all the elements of your system right.

For more information go to: www.ellexus.com

RosemaryFrancis,
Good comments. That is exactly what I do with my testing. I also document my methods like you state, General interface, I call stm interface, in the documentation of the VHDL Test Bench package linked in my previous post. The document contains a description of model writing that includes the stm interface.

I have started a Blog at:
VHDL Test Bench for FPGA/ASIC Verification: Introduction

Feel free to add comments as I post up usage tips for the VHDL test bench package. They will include exactly what you are talking about, plus the VHDL code.

Sckoarn