Gate oxide breakdown voltage conditions

Hi,

I am working on a Switched capacitor based DC-DC converter in 45nm technology using cadence. I have got a question about the gate oxide break down voltage. What are the conditions to prevent gate oxide breakdown?

I read somewhere that the gate-source voltage should not be higher than the gate oxide breakdown voltage. If thats the only condition can i use VDD higher than gate-oxide breakdown voltage in circuit.

I am using nmos1v in 45nm cadence technology. What is the gate-oxide breakdown voltage for this MOS.

thanks

viperpaki007 said:

I am using nmos1v in 45nm cadence technology. What is the gate-oxide breakdown voltage for this MOS.

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Find this in your PDK docu. Or simulate the breakdown!

i used nmos1v for my simulations, Which i suppose has 1V gate oxide breakdown voltage. but the simulator did not complain anything about gate oxide breakdown for input voltage and VDD of 1.8V. I tried to change the input voltage to 10V and then it was complaining.. Its quite strange for me....I also dont know what are the actual conditions for gate-oxide breakdown. Whether it is the gate voltage or gate-souce voltage which should not be more than the gate oxide breakdown voltage...

You need to know the maximum allowed voltage for the oxide. The breakdown voltage is usually ~3x the max allowed voltage.

Running near the breakdown voltage will result in very short lifetimes.

Actually any voltage difference between the gate and any region below the gate mustn't be higher than the gate oxide breakdown voltage, so this concerns all voltages Vgb, Vgs, Vgd.

For 45nm processes with a std. gate oxide physical thickness of 1.1nm = 11Å, the "official" (hard) breakdown is around 4V - if the gate oxide is SiO2 resp. PNO (Plasma Nitrided Oxide). See your simulation model file, at which voltage your foundry decided to utter an error message - or simply try it by DC analysis.

Soft breakdown, however, already starts @ Vgx ≥ VDD = 1V , which means tunnel current through, and trap generation in the gate oxide, generating stress for the gate oxide and worsening its isolation capability over time, and - especially - at high temperatures. See e.g. this link for more info about this.

To avoid gate breakdown, pls try series connected poly resistor to limit current and connect a gate-grounded NMOS to this node to clamp the gate voltage.

thanks for the info..i got the idea now..