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What's the relationship between PLL bandwidth and free-running frequency?

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eegchen

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hi,

How to balance the PLL bandwidth with free-running frequency?

I saw people said that usually PLL bandwidth is much less than free-running frequency, WHy?


Thanks
 

because free running frequency of the vco is typically in the 300 mhz to 20 ghz range, and trying to get the pll control loop to have more than 5 mhz of bandwdith will usually end up in an unstable condition due to delays and parasitics.
 

or you need to use a band step gain block and syncro block band stepping so the referance must be post proceed the gain loop band width /10 or /100 or /100

has to be harmus... level

and the gain block is for the loop filter also variable notch...

300mhz to 20ghz is a big leep and has to be banded

then there is stepping needed and you need to do this both at the loop and the referance

---------- Post added at 05:33 ---------- Previous post was at 05:28 ----------

you can use a simple 4059 or even 2 to achive this with just two external ic's /10
and two vco

the ratio = 1/n where 1 = input to loop and n = 1/(ipl/v)

loop vector does come in to it

most people use low freq to give accurate hi freq or in our case sshf fixed
 
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Hi Biff44,

Thanks. Could you give some more detail explanation why PLL become unstable for higher bandwidth?
 

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