keremcant
Member level 5
hi,
I draw a circuit in schematic editorc in xilinx and it has a clock. but when I try to generate programming file for fpga, I get this warning:
WARNING:Route:455 - CLK Net:XLXI_29/divided_clock may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
and than my circuit does not function on the fpga. I guess this is a basic warning, since I am a basic learner and my circuit is a small and not complicated. but why do I get this warning?
thanks.
I draw a circuit in schematic editorc in xilinx and it has a clock. but when I try to generate programming file for fpga, I get this warning:
WARNING:Route:455 - CLK Net:XLXI_29/divided_clock may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
and than my circuit does not function on the fpga. I guess this is a basic warning, since I am a basic learner and my circuit is a small and not complicated. but why do I get this warning?
thanks.
