M:ak
Newbie level 1
Hi ,
I am a relatively new , to the ASIC flow . I am looking to understand , Clock Tree Synthesis . I know why it is done theoretically , but i have a few specific queries , kindly help me understand the same ->
1. if we have clock with say a latency { max - min insertion delay } = 250ps
a skew of 40 ps
compare this to a strategy , where the clock has a skew of 10 ps but latency of 500ps . Which is a better clock strategy ?
a) Kindly explain , with reference to OCV ?
b) power utilization .
2. what can be done to contain fanout violations post the clock tree being built ? is cloning , decloning the only work around . Can anyone suggest a flow with SOCencounter .
Thanks
I am a relatively new , to the ASIC flow . I am looking to understand , Clock Tree Synthesis . I know why it is done theoretically , but i have a few specific queries , kindly help me understand the same ->
1. if we have clock with say a latency { max - min insertion delay } = 250ps
a skew of 40 ps
compare this to a strategy , where the clock has a skew of 10 ps but latency of 500ps . Which is a better clock strategy ?
a) Kindly explain , with reference to OCV ?
b) power utilization .
2. what can be done to contain fanout violations post the clock tree being built ? is cloning , decloning the only work around . Can anyone suggest a flow with SOCencounter .
Thanks
