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Setup Time problem in a flop consists buffer in clock of that flop.......

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madhunandyala

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Hello Friends,

I am giving a problem which has recently asked me in an interview. Please if u find the answer let me know. Thank u.......

Prob: There is a flop of internel setup time 100ps. and the clock line to that flop has a buffer(Inverter+Inverter -- having both 20ps each delay). So totally 40ps delay in clock arrival. The question is what will be the total setup time considering the flop and the inverters. Please give elaborated answer guyz.........Thank u.....

PS: There it has not mentioned about the clock frequency.
 

Hi,

The setup time for the flop doesn't change. The data still needs to be stable 100ps before the clock edge hits the flop.

Assuming the flop that created the data has zero delay on its clock line, you have a "fast" clock flop talking to a "slow" clock flop. The data can now arrive 40 ps later and still meet setup requirement.

The net effect is that the flop "appears" to have a setup time of 100-40=60ps.

In this scenario, fast-to-slow, I would watch out for hold violations.
 

Thank you for ur kind information.

But there is no specification of the clock ......and i have been asked to calculate the set up for the total circuit. Is there any possibility to calculate the setup time for the whole circuit instead of a flop?? Please clarify..........
 

Read this Tutorial.
This might be helpful for you.
 

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Hi, the clock frequency does not matter (unless it is so fast that you can't build your chip).

The relationship between the clocks of "communicating" flops does matter. You have a delayed clock. The delayed clock helps your setup requirement by allowing the data to change later than if the two clocks had no delay between them.

The setup of your flop is fixed (in this type of question they are not talking about edge-rate or PTV effects).
 

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