Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

DRAM sense amplifier layout

Status
Not open for further replies.
E

eladla

Member level 4
Joined
Jul 10, 2009
Messages
78
Helped
15
Reputation
32
Reaction score
12
Trophy points
1,288
Activity points
1,817
Hi,
I am trying to layout a DRAM sense amplifier.
I already have a layout, but I`m sure it`s not optimal,
since I made it without a refrence. It barely fits within the cell pitch.

Can someone please point me to a refrence design or some other such resource?

Thank you!

Edit: I`ll elaborate on my problem. I attached the layout I have so far.
The two pmos transistors are cross-coupled (source to gate) and the sources are connected to bitliens. Now I need to connect both drains together and to an input signal, but without connecting to the bitlines.

How can I do this? Any ideas?
 

Attachments

  • sense_amp.pdf
    122 KB · Views: 63
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top