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Relation b/w Time period and hold time, setup time and Clock-to-Q Time

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mwasif_ciit

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Hi,

For a given storage device (FF, Latch), What is the relation between time period of clock and Hold time, Setup time, Clock to Q time?

thanks. :)
 

Hi,

Typically the data input of a flop needs to be valid (static) before the clock goes active (the setup time), and the data input needs to stay valid (static) after the clock goes active (the hold time).

The setup and hold requirements for flops are there to be sure the Master, of the Master-Slave configuration, is able to capture the data without going metastable.

The timing diagram showing clock and data relationships can be found here:
Flip-flop (electronics) - Wikipedia, the free encyclopedia

The clock-q time is how long it takes for the new data to be "seen" (propagate) on the output of the flop.

As you crank up the clock frequency, you will see a point where the data going from one flop through some combinational logic to another flop starts to violate the setup and hold requirements of the receiving flop. This clock frequency is the frequency where your circuit breaks.
 

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