[SOLVED] Question about turning on an op amp not going on saturation

Greetings to everyone, this is my first post.
Sorry for my bad english, I'll do my best to be as clear as possible.

Question is: how can an op-amp (for example in the noninverting configuration) go in the linear range of its I/O characteristic after being powered up?
Experience clearly demonstrates that noninverting op-amps work obviously, but if I trace the (hypothetical) steps occurring immediately after the power-up, it seems to me that it should go into saturation and remain there.

So imagine an op-amp in noninverting config, and let's call V+ and V- the input and Vo the output voltages. Be R1 and R2 the two resistor forming the feedback so that voltage gain would be 10 (β=1/10). Power supply erogates +15V and -15V , so if output exits the interval (-15V, +15V), the amplifier saturates.
On the noninverting input V+ is a battery of +1V. So I expect that at the end of the transient following the power-up, I shall see +10V at the output.

So let's turn on the power and let's see what I imagine should happen : V+ = 1V and V- = 0V => Vo saturates at +15V;
the feedback divides this tension by 10 and so V- = +1.5V.
Now at the two op-amp input we have V+ = +1V and V- = +1.5V, and so the difference is -0.5V; this difference will drive the output of the op-amp in negative saturation (the open loop gain is so high that the voltage difference between input leads of an op-amp configured in negative feedback so that it should work in linear behaviour is of the order of tens of microvolts).
This negative output is divided by 10 and feed back to the V- terminal and so on.
So, as you can see if this analysis was true, the op-amp would never go in its linear zone.
Could someone of you please enlight me over this issue?
Thanks in advance.

I am not sure, but I think you are describing an oscillator, or in other words an unstable amplifier. You are assuming that the output flips from one extreme voltage to the other and the inputs do the same with no time lag. In reality the time lag allows the opamp to stabilize on its way from one extreme to the other.

Keith

Thanks for your reply.
Yes, I am assuming that every new voltage value at the output propagates in no time to the inverting input of the op-amp, and I still think it's a realistic assumption.
Think about what the output pin sees looking back towards the V- input: a voltage divider with maybe a tiny capacitance in parallel to the second resistor. The signal should propagate almost at the speed of light while there should certainly be a propagation delay in the opposite direction (while the op-amp is being traversed).
So I presume that that time difference makes my assumption still valid.
On the other hand, wouldn't seem strange to you a circuit design that works thanks to its non-predictables "inefficiencies" such as time lag, of which none of the book I read so long makes mention?

What about the time lag from the input of the opamp to the output?

Keith

Even keeping in count the "direct" time lag, I cannot figure out HOW it should work in the direction of putting the amplifier in the linear interval of its I/O characteristics (starting from saturation).
Maybe I should draw a time diagram similar to those used in the timing analysis of digital design to try to see if your thesis convinces me.

Seems like you intend to reinvent electrical network theory? Instead of assuming hypothetic properties of OP circuits, you may want to analyze the behaviour of a real device. E.g. regarding the below assumption:

So, as you can see if this analysis was true, the op-amp would never go in its linear zone.

Click to expand...

The output voltage of real OP will take a considerable time (at least several ns, up to µs with general purpose types) to slew between the rails in an input overload condition. Just a simple hint that nothing is like in your speculation.

You should preferably start with an exact small signal analysis of OP circuit behaviour, particular stability conditions. Large signal behaviour is more complicated, and you are actually able to design circuits that are conditionally stable, but start to oscillate after a stimulus that exceeds the linear circuit range. But it's not a case of simple saturation.

FvM said:

Seems like you intend to reinvent electrical network theory? Instead of assuming hypothetic properties of OP circuits, you may want to analyze the behaviour of a real device.

Click to expand...

Obviously you are right about the fact that I must aware of not pretending that nature conforms to my theories about how it should work
But my question could be read as follows:

can someone please point to me where my model is erratic?

You and keith1200rs both introduce the question of time delay and that can be the key to the answer I am searching, but I'd like an answer like this:

"your model doesn't consider this property of real op-amp and at this link you see why and HOW it makes the difference and HOW it explain the behaviour of real op-amp in the scenario you illustrated or in a similar one"

OR

"I don't know why it happens and how to explain to you. You should consider googling better"

As I am writing this post, I've found **broken link removed** one, in which the author takes the formal way to explain his perplexity about the same phenomenon, but he gets no answers.

Hi Tadde,

in addition to the facts mentioned already by keith and FvM (time delay) I like to mention that the task of the feedback path is to allow a stable operating point within the linear input-output characteristic of the opamp.
What means "stable operating point"?
Answer: An output voltage which fulfills the classical amplification formula for linear operation:
Vout=Aol*(Vin,p-Vin,n) with Vin,n=Vout*k; hence: Vout=Vin,p/(1/Aol + k)
(Aol=opamp gain in open-loop condition).
With this in mind we can imagine the following steps (based on a very small time delay between input change and output reaction) for *Vsupply=+/- 15 volts; *Feedback factor k=0.1 ; *Vin,p=+1 V.

1.) t=0 (power switch-on): Vin,diff=Vin,p-Vin,n=+1V and hence: Vout=+15V.
2.) t>0: Question: Vin,diff=(+1-1,5)V=-0.5V and hence: Vout=-15V ??? Answer: No !
3.) Explanation: During the transition from Vout=+15V and (perhaps) Vout=-15V the ouput voltage crosses the only point which fulfills the above mentioned stable condition, for example with Aol=10000: Vout=+1V/(1E-4 + 0.1)=+9.99V.
4.) This means: As soon as the output reaches Vout=+9.99V the transition from Vout=+15V to lower (and negative values) stops at the only point which fulfills the mentioned criterion.

Does this explanation help a little?
LvW

When you start to study a phenomenon in natural or engineering science, why don't you try to understand the existing models, that can be found in text books rather than postulating your own model and asking why it's wrong?

A simple mode but useful OP model would be a differential gain stage, a first order low-pass and a voltage limiter. For a classical LM741, assume e.g. a gain of 200e3 and a low pass cut off frequency of 5 Hz, resulting in 1 MHz gain-bandwidth product (GBW). Additional low-pass poles and possibly a slew rate limitation at the output would bring the model very near to a real OP device. You can apply your scenario to the model and observe it's behaviour.

Besides pencil-and-paper method, a free circuit analyzer, e.g. LTSpice can be helpful for the analysis.

LvW said:

3.) Explanation: During the transition from Vout=+15V and (perhaps) Vout=-15V the ouput voltage crosses the only point which fulfills the above mentioned stable condition, for example with Aol=10000: Vout=+1V/(1E-4 + 0.1)=+9.99V.
4.) This means: As soon as the output reaches Vout=+9.99V the transition from Vout=+15V to lower (and negative values) stops at the only point which fulfills the mentioned criterion.

Does this explanation help a little?
LvW

Click to expand...

Your qualitative explanation does convince me, thanks. I was thinking of an output voltage that assumes its final values without considering the continuity between them. Note that in your explanation there's no need of the time delay issue between input and output.
So here's (one of) the flaw in my poor model: I was not considering the continuous nature of the output voltage (as any other physical quantity).
Thanks again to everyone, expecially to you.

---------- Post added at 14:56 ---------- Previous post was at 14:53 ----------

FvM said:

When you start to study a phenomenon in natural or engineering science, why don't you try to understand the existing models, that can be found in text books rather than postulating your own model and asking why it's wrong?

Click to expand...

That's what I did. The only problem was that I though my model was right, or better said, I didn't understand where it failed representing the aspect of the reality I was interested in.