DFT & Synthesis: Scan clock inversion and non-unate warning

All,

I am synthesizing a basic design with three clock domains and the occasional negedge flop. To make reordering not an issue for negedge flops, I invert the clock with scan_mode. The scan_mode signal is generated from a flop within the design. The tool reports

at many points throughout the synthesis and scan insertion process. There is very little mentioned about this on Solvnet.

My questions:

1) Does this cause the tool to needlessly iterate and burn area, attempting to meet half cycle paths?
2) If so, what is the best way to fix it? I invert two different clocks in the design. At one point in my synthesis, I must have added a constraint or changed the design such that one clock stopped reporting a unate-ness warning. I'm not sure what I did, and it's very confusing!

Thanks!

you don't want to generate scan_mode by a flop since that flop may get 0 or 1 depending on the logic cone contributing to that flop, or even worse if that flop is on the scan chain.
You need to make scan_mode and scan_enable externally controllable.

Some experienced ppl do use DFF to generate scan mode signal, so that scan mode signal's transition can be at speed.

You'd better not to use registers with different clock edges. Instead, you should generated a inverted clocks before the negedge register and then this register will be implementation into a posedge register.

Creese said:

You'd better not to use registers with different clock edges. Instead, you should generated a inverted clocks before the negedge register and then this register will be implementation into a posedge register.

Click to expand...

Yes, that is what I do. All registers are posedge, with negedge clocks created before they are used.

Also, the test_mode register in question indicates that a key signature has been written. It *cannot* be set or cleared without mantipulating an external pin which will be controlled by the patterns, removing it from the logic cone.

Back to my original question about unate-ness.... is this a concern? How should I consider the warning?

You should be able to have the scan insertion tool add lockup latches before the negative edge scan flip-flops on the scan path. That would be a better solution than to invert the clocks for these flip-flops.

Have you ensured that scan_mode does not change when the chip is clocked? You might have problems if a the scan_mode signal changes for a FF while it is clocked.

I suggest that you have each clock domain use a separate and independent clock pin in test mode. That way you can ensure there are no cross clock domain timing issues. Just clock each domain in a different cycle of your test.