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Please help me analyze this circuit for possible Timing Violations

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curious_kid

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Hi All,


I am attaching a circuit diagram.

This circuit is basically trying to generate a double pulse for atspeed test vector generation. It could be for anything else, so don't worry about the functionality


The way it works is there is an asynchronous signal force_2_pulse, it is synchronized using a 2 flop synchronizer.

Whenever this signal comes, the pll clock is used to generate two high speed pulses for at-speed testing. This clock comes out as clock.

Sel 1 and Sel2 are also chip level pins and there selection determines whether the 2 pulses from pll output will go the logic ahead or normal slow speed clock

My question to you guys is

1. Could you please help me analyze what could be possible timing violations in this circuit? Like glitches, setup, hold violations.


Thanks a lot
 

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  • at_speed.jpg
    at_speed.jpg
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are you already synthesis & PR this code ? and found any specific violations?
 

Wherever you gate a clock with a signal driven by the same clock is a potential glitch source. In your case, the last NOR gate can cause a glitch if the clock reaches NOR gates later than flop output does.
 
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    paragn

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Thanks lostinxlation, is there some possibility of some violation because of the asynchronous signal force_2pulse

---------- Post added at 11:18 ---------- Previous post was at 11:16 ----------

No RCA, not yet but just want to understand the possible violations/solutions that could occur after PR
 

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