moonnightingale
Full Member level 6
My code is this
//Verilog Model User Defined Primitive
primitive udp_3input(d,a,b,c); // this is line 2
output d;
input a,b,c;
table //Defining Truth table
/* Defining Table
a b c : d */
0 0 0 : 0
0 0 1 : 1
0 1 0 : 0
0 1 1 : 1
1 0 0 : 0
1 0 1 : 1
1 1 0 : 0
1 1 1 : 1
endtable
endprimitive
module circuit_with_udp(D,A,B,C);
input A,B,C;
output D;
udp_3input (D,A,B,C); // this is line 21
endmodule
I am receiving this error message after synthesis
ERROR:HDLCompilers:1 - primiti.v line 2 User defined primitives are not supported
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: '('
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ')'
//Verilog Model User Defined Primitive
primitive udp_3input(d,a,b,c); // this is line 2
output d;
input a,b,c;
table //Defining Truth table
/* Defining Table
a b c : d */
0 0 0 : 0
0 0 1 : 1
0 1 0 : 0
0 1 1 : 1
1 0 0 : 0
1 0 1 : 1
1 1 0 : 0
1 1 1 : 1
endtable
endprimitive
module circuit_with_udp(D,A,B,C);
input A,B,C;
output D;
udp_3input (D,A,B,C); // this is line 21
endmodule
I am receiving this error message after synthesis
ERROR:HDLCompilers:1 - primiti.v line 2 User defined primitives are not supported
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: '('
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ')'