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why user defined primitive not workingin Xilinx ISE 6

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moonnightingale

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My code is this

//Verilog Model User Defined Primitive
primitive udp_3input(d,a,b,c); // this is line 2
output d;
input a,b,c;
table //Defining Truth table
/* Defining Table
a b c : d */
0 0 0 : 0
0 0 1 : 1
0 1 0 : 0
0 1 1 : 1
1 0 0 : 0
1 0 1 : 1
1 1 0 : 0
1 1 1 : 1
endtable
endprimitive
module circuit_with_udp(D,A,B,C);
input A,B,C;
output D;
udp_3input (D,A,B,C); // this is line 21
endmodule

I am receiving this error message after synthesis

ERROR:HDLCompilers:1 - primiti.v line 2 User defined primitives are not supported
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: '('
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ','
ERROR:HDLCompilers:26 - primiti.v line 21 unexpected token: ')'
 

Always pay attention to the first error message, as the others are probably follow-ups.
User defined primitives are not supported
Refer to the "Verilog Language Support" specification of your compiler version. ISE 6 is a very old version, but as far as I'm aware of, Verilog UDP is still unsupported in most recent ISE12.
 

Thanks FVM for first line explanation
Can u tell me some other simulation tool which is good and supports UDPs
Can u extend me more help in Xilinx ISE Software if i PM u. thanks
 

I'm not using Xilinx tools myself, I'm only keeping the documentation for reference. Their are many edaboard users who are quite familiar to ISE and XST.
 

UDPs are not synthesizable. That is why xilinx tool is reporting error.
 

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