Help me solve Xilinx ISE error: HDLParsers:1305

HI

I am trying to synthesise the code in xilinx ise it gives me the following error


ERROR:HDLParsers:1305 - "C:/Downloads/Motionestimation/me.vhd" Line 60. result of operator > is not static.

does anyone know about this error?

Re: Help about error

what is line 60? what are the declarations of the arguments/functions on line 60?

Re: Help about error

i am attaching the code for me

Re: Help about error

well, thats not the correct file, or you've changed it.

in anycase static in context means constant.

your code uses a generate without a _declared_ constant argument. This means either a generic, or a constant. A signal/port that will be connected to constant is not enough.

A generate is intended to duplicate or add hardware to the design.

You've chosen a project that requires a bit of extra understanding because the synthesis tool needs to be able to infer efficient hardware. I don't believe you have enough experience with FPGA development to appreciate these issues. Certainly you are not familiar enough with VHDL to be able to solve these issues. Starting with such a design will make things very difficult.

As you can see, you started with inefficient, but valid, VHDL code. When implementations issues arose, you moved to something that could have worked, but didn't have a good enough understanding of VHDL to get everything working. After that you just reverted back to the original approach, except you started blindly trying every language construct you could find in hopes that one would work. The results with impure functions, instantiating components withing a process, and using generates within a process haven't provided good results. If you learn about "procedures" you will also have poor results.

If you instead start with a simple project that works, then add on to it, you'll hopefully begin to realize how VHDL is intended to work. You'll also be able to determine when FPGA resources become an issue -- after each sucessful build you'll see the resource utilization. when you have 10% of the design finished, and the FPGA is using 50% of the BRAMs, its likely the approach you've taken won't scale up by a factor of 10.