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Using non blocking assignment for sequential code in Verilog

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hallovipin

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Hi,
I am new to verilog. Whatever material I have across over a month , all suggest that we should always try to avoid using blocking assignment.
I know the literature says that we should use <= for sequential and = for combinational.
But can somebody make it clear how to write given code with the help of <=

module (a,b,c,d,step1,step2,final_value,clk);

input [7:0] a,b,c,d;
output reg step1, step2, final_value;

always @(posedge clk) begin
step1=a+b;
step2=step1+c-d;
final_value=final_value+step2;
end
end module

now problem is if we use <= in simulation I dont get proper values of final_value.

how to use <= at a place when calculated value of the above expression is fed back to the next expression; (as shown in code)

They say that <= prevents generation of race condition.
But what I found that if I carefully place = in the code it works better.

Why is it a SIN to use = in Verilog.

Please suggest can I use <= for above software.
 

For calculation of intermediate results, you obviously need blocking assignments.

You possibly noticed, that the intended operation can be written into a single assignment, omitting the step1 and step2 variables.

Using non-blocking assigments, the final result is calculated in the third clock cycle, step1 and step2 are acting as pipeline registers.

I won't say that this a wrong result, pipeline operation can be quite reasonable in some cases.
 

    hallovipin

    Points: 2
    Helpful Answer Positive Rating
This is correct.

A big issue with intermixing blocking and nonblocking is when you get code like:
a = b + c
b = c + a
c = a + b

where another variable is needed. In VHDL it becomes an issue as "variables" have no non-blocking assign.


for verilog, the issue they are referring to would be the one where x is defined in another clocked process, and y = x + c is defined in this clocked process. if the simulator evaluates this process first, then y = old x + c. if it evaluates the other process, then y = new x + c.

further, it might not ever evaluate the processes in a predictable order. Thus it is helpful to use <=, so that all of the events associated with posedge clk can be processed.
 

Re: Using non blocking assignment for sequential code in Ver

who said you that '=' is a sin in verilog?? you can write the same code as....

module (a,b,c,d,step1,step2,final_value,clk);

input [7:0] a,b,c,d;
output step1, step2;
output reg final_value;

wire step1=a+b;
wire step2=step1+c-d;

always @(posedge clk)
final_value<=final_value+step2;

end module
.....................................................................................................
Actual rule is that its better to keep combinational logic and registers seperate... as i did...
 

Re: Using non blocking assignment for sequential code in Ver

I thank all you gentlemen for looking into this. But I have some queries for each of you.

@ FVM

If I replace all the = with <= in above code, would the result be same (Let there be a delay of 3 clock cycles). I mean I wont mind having dely in values of final_sum but they should be in same order which I am getting with blocking assignment.
example if with blocking final sum is = 1,2,3,4,5,
then with non blocking it should be 1...2...3...4...5 (count one dot '. ' as one clock cycle)



@permute

But if all the statements with = assignment are placed in proper order, the next statement will not get executed untill first is evaluated and assigned.
So how eill there be unpredictability.


@umair ali

wire step1=a+b;
wire step2=step1+c-d;


these statements are out of always block.. so we never know which one of these will get executed first.

also if clk is in sensitive list the other arguments are need not to be there since at clk is fastest signal which will trigger always block each clock cycles evaluating newest values of all variables.

this trick is useful if Clk is we are writing purely combinational circuit.

plz clarify.
 

the issue is with:

always @ (posedge clk) x = y;
always @ (posedge clk) y = z;
always @ (posedge clk) z = x ^ (~y);

this is a simple example. but what if these statements were in different modules at different levels of hierchy? For synthesis, it probably won't matter, but for sim it can become an issue. (and even if they are in the same module)

If "posedge clk" is encountered, then the sim will do one of 6 different orderings of these statements. each ordering will result in different values for x,y,z. I'm not sure if synthesis allows this case, as its not clear what the user actually wants.

The ordering may not be bottom to top, or top to bottom, or even be consistant. Even if there were some rules, the fact that they could be in seperate levels of hierchy would make the rules very hard to use.

now if non-blocking statements are used, none of these values changes until after all of the always blocks are evaluated. This makes the order of evaluation unimportant.


Thus, the output of a clocked process should use the non-blocking assignment.

For combinatorial processes, it can be beneficial to use blocking assigns. eg:
always @ (a, b, c) begin a <= b; d <=c | a; end
in this case, if b changes, then:
evaluate, find a = b. d is unchanged
notice "a" has changed.
evaluate, find a unchanged, d is updated.

For combinatorial logic, the evaluation/re-evaluation process can continue, but will eventually finish -- unless there are combinatorial loops.

with blocking assigns, the "a" input is no longer needed, and a change to b will result in a change to d within the first evaluation of the block.


Now, for clocked processes, "=" has another downside. if x = y is inside a clocked process, then x cannot be used blindly in any other clocked process -- as before, the simulator can evaluate the assigning "always" either before or after x is used.


For the case where you ONLY use the intermediate results within the clocked process AND you correctly use the blocking assigns, it will work and sim correctly. This is the same as the use of "variables" in VHDL -- where "variables" can only use blocking assigns and can only be used in a single process.
 

Re: Using non blocking assignment for sequential code in Ver

@ permute
yes.. u r right. I know that thats why I am using all these assignment in a single always block.

Also multiple assignment to a single variable in different always blocks is not allowed by ISE. so there is no such problem.

Am I safe Now???

One more thing. If My after synthesis simulation (after place and route simulation) is correct can this guaranty that it will work perfactly in hardware also. I mean to say is there any chance of getting wrong result even if u have got it right it in post synthesis simulation. (Of course I will take care of timing constraints )
 

hallo:
That should be fine. As I've mentioned, there are other reasons why it is considered bad practice to mix the two in the same process. It can make the code harder to read/write as the code complexity grows.

(also, in my example, each assignment was within 1 always block, but the reg was read from multiple always blocks.)
 

    hallovipin

    Points: 2
    Helpful Answer Positive Rating
Re: Using non blocking assignment for sequential code in Ver

I would prefer to discuss blocking versus non-blocking assignment usage with design examples, where it's actually serving a purpose to use one or the other. The above examples mostly aren't good in this regard.

Personally, I'm mainly writing VHDL, using Verilog only on customers request or when porting existing code. As mentioned above, VHDL has VARIABLE as equivalent to Verilog blockings assignments, but their visibility is limited to a single process. But they have a similar usage as Verilog blocking assignments, they are used for intermediate results and signals that are re-read during a single clock cycle.

To understand what blocking versus non-blocking actually means, it's good to remember that we are dealing with a HDL (hardware description language). Try to sketch the hardware that's defined by both constructs.

I think, that those cases, where registers are assigned by blocking statements, re-read in the same clock cycle and also used to hold the values across a clock cycle are causing most confusion. They should be better replaced by clearer constructs.

In my opinion, the topic has been almost exhausted by the well-known cummings paper,

I don't see much use in retelling the examples, that have been discussed systematically in this paper (and many Verilog text books, too).
 

Re: Using non blocking assignment for sequential code in Ver

it dose matter when you simulate your design.. but it will generate perfect results when you synthesize it.. one more thing, the book you are referring is samir palnitkar( i guess) try another book.. FPGA programming by Chu
 

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