4:1 MUX using only 2 4-input LUTs only

How to implement a 4:1 MUX using just 2 4-input LUTs?

Is this possible without using any other built-in cells (like MUXF5, MUXF6 in Xilinx Virtex FPGAs)? How would the LUTs be configured as if it is possible?
I have read that this is possible, by using all the 4 pins of the each of the 2 LUTs, but not sure how exactly.

Thanks

2 4 -input LUT means, you can consider it as ram has 4 row and 2 column means 2X4 bit memory.

Now for 4:1 mux 2 selec line is needed. so select lines will be your memory (LUT) address. and out put data means read data will be your out put of mux.

HTH

varthurravi said:

How to implement a 4:1 MUX using just 2 4-input LUTs?

Click to expand...

Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs?

Under those conditions, the problem is solvable with the caveat that switching between mux inputs that are both high may cause a low pulse on the output, and vice versa. Most simply-implemented muxes will only have one glitch or the other.

Clearly one LUT needs to have an input from the other, meaning one LUT has four inputs available and one has three. There are six signals that need to be handled, so one signal can be duplicated on the two LUTs. Figure out which signal needs to be duplicated, and figure out how the first LUT can always say something that will be useful to the second LUT.

Further hint: The two LUTs will be functionally identical, except that the meaning of one of the inputs will be inverted.

Further on this topic, this is the clue I got to resolve this (refer snap-shot of how the LUTs are connected, where A, B, C, D are inputs and S0, S1 are the MUX-Selects with S1 being MSB).
Now, I have to find out how both these LUTs are configured such that it works as a 4-input MUX.

Thanks to everyone who are trying to help me.

So, how should I code my VHDL/Verilog to implement the 4:1 MUX as in the snap-shot?
The usual way of coding 4:1 MUX results in 3 LUTs where each LUT is configured as 2:1 MUX (mapping a 4:1 MUX as 2:1 MUXes) .

What information does Lut2 need when S1 is high? What information does it need when S1 is low?