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How to set constraints for two outputs

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vkchau

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Hi, anyone help me what constraints should I set to achieve below:
1. For example, my design on Altera FPGA runs at 100MHz, and have two outputs. I want two signals to active at the same time. I mean the time difference between them is less than 1ns. Could I achieve that?
2. If yes, what constraint should I set, between two signals, clocks...?
Thanks
 

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