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Not if you want full rail to rail output. Fets would stop conducting before output reach Vss or Vdd. The source of NFET needs to be Vssed for full swing down to Vss , and the source of PFET needs to be Vdded for full swing upto Vdd. I forgot the exact formula, but it is in electronic books. Look at how FET works, especially when FET conducts(Its the function of Vg Vs, Vd, and Vth).
Not only it will not swing to the rails but also it will have a dead zone around the middle 0.5(Vdd+VSS). In other words this is a class A (at least) stage. If you want reasonable linearity in the output following the input you'll not get it with this circuit.
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