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How to design this LNA? [Gain: 8 dB, NF: <1dB, IIP3: 10dB

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liaodongyuan

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atf54143 amplife

f:1850-1910MHz
Gain:8dB
NF:<1dB
IIP3:10dBm
a single-stage balanced amplifier(I use two ATF54143)

To meet the low gain,I add a Pi Resistor network,but the NF become worse(about 1.2dB).Can you help me?
 

how to design this lna?

you shouldn't add any resistive network at the input of the amplifier as they increase the noise. If you want to reduce the gain, add the pi resistive network after the amplifier. But the expense is the P1dB is lower.
 

Re: how to design this lna?

How about using inductive source feedback to lower the gain retaining good linearity and low noise figure?

You can also get simultaneous noise and gain matching.

I shall attach the reference for series feedback LNA.

Good luck.
 

Re: how to design this lna?

Thanks for your replies!

activewei:In fact I add the resistor network at the output of the amplifier, so that the NF just get a little worse.

dhlee:I haven't enough points to download the file.Can you send it to my emails:liaodongyuan@hotmail.com or liaodongyuan@sina.com ?
 

how to design this lna?

anybody have design a LNA in SiGe technology?
 

Re: how to design this lna?

liaodongyuan said:
f:1850-1910MHz
Gain:8dB
NF:<1dB
IIP3:10dBm
a single-stage balanced amplifier(I use two ATF54143)

To meet the low gain,I add a Pi Resistor network,but the NF become worse(about 1.2dB).Can you help me?

Hi liaodongyuan
you have not specified all the specs. Pout, Gain; cause i do not know why you have opted for a balanced ampifier; i feel the device you have chosen is good enough to give you a gain of around 15 dB with a near 1dB NF ( the device Fmin itself is around 0.42 dB at 2 GHz and biased at 3V,40mA) . To reduce the gain you may change the bias appropriately (use the nonlinear model given in the data sheet); to get a better noise figure DONOT use any resitances in the input match (it would be better is you use inductors for both the gate & drain biases); Also i suggest you use a degenerative feed back at the source to obtain a better impedance-noise match & this wil also reduce the gain and improve stability! if required you may use a small resistor in series with an inductor (in shunt) for the output match( this will also stabilise the ckt)
hope this info will help you to initiate the design
8)
 

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