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Layout dependance of the matching parameters

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adnan

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The matching parameters document provided by the foundry states that these parameters are for "the matching of two identically designed elements located close to each other".

It is logic to think that two large transistors laid out in 3 ways: One close to the other, interdigitated, or centroide, will not have the same matching parameters. The third will have the best parameters followed by the second.

Does any one can help in giving rough estimate of the difference of matching parameters for the 3 ways of layout?
A practical reference is also appreciated.
The technology is 0.35 um.
 

Of course in 3 different ways of layout transistors have different caracteristics.
 

Any idea by how much Delta(VT) differs in the 3 cases?
 

Why would you want to estimate the effects of doing it wrong,
than do the right thing?
 

dick_freebird,
The reason is that the mismatch parameters from the fab is for "the matching of two identically designed elements located close to each other" and not for interdigitated, centroide or waffle.
My layout will be done interdigitated, centroide or waffle. So I would like to convert the mismatch parameters from the fab to this types of Layout.
 

I have not come across fabs ever being very specific about mismatches beyond the normal matching parameters. I suspect they don't bother finding out what the mismatch is for transistors not close together, for example.

I have heard it said that the matching of devices close together is no better than devices further apart. See Hans Camenzind's online book about analog chip design - page 17-9. http://www.designinganalogchips.com/

Here is a bit of it:
Over the years a number of rules have accumulated around
analog design, especially concerning matching devices. For example,
most designers believe that matching devices should be intermingled
and as close together as possible, because the diffusions or implants
have gradients, i.e. vary gradually in depth or concentration over the
area of the chip.
A few years ago I had an opportunity to examine this. I
measured the matching of adjacent devices and compared that with
devices which were farther apart. To my surprise I found no
statistically valid difference in matching for a distance of up to 2mm.


There are plenty of people who will disagree with this view, I am sure, but I have not seen any evidence to refute his conclusion!

Keith.
 

I see many wafers with substantial gradient in VT and other
attributes. But scaled to sensible distances the numbers
become less than the statistical mismatch floor. For example
100mV across wafer (at, say, 10cm spacing between
WAT keys) or 10mV/cm becomes 1uV/um.

Now, if you're talking a part with any kind of on-chip power
dissipation, the spacing also plays with the thermal gradient
if you are laid out longitudinal. We used to take great care
to orient pairs orthogonal to the expected thermal gradient
back when you'd design one op amp and put in a can. Of
course large, multi-heater, cell based designs make this more
of a headache. But it is worth considering in power products.
 

The mismatch etc. is very dependent on the foundry and process technology.
At 65nm etc, definitely you want interdigitize (or common centriod) along with dummies on both sides to prevent well stress.

I think at .35u, it might not make much difference. Foundries don't do a good job of documenting the difference in mismatch between different layouts. So we just end up doing what we learnt at school (common-centroid). CYA :)
 

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