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single cycle processor mips 32 bit (data memory)

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funjoke

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i am working with the single mips cycle processor data memory part ,and i am facing problem with the verilog of data memory ...here is my code ...


// Data memory
// It doesn't have a memory read output
module DM(dataread,clock,memwrite,addr,datawrite);

input [31:0] addr,datawrite;
input clock, memwrite;
output [31:0] dataread;

reg [31:0] memcell [0:3]; // 4GBmemory cells


assign dataread = memcell[addr[6:0]];

always @(posedge clock)
begin
if (memwrite == 1) memcell[addr[6:0]]=datawrite;
end

endmodule
 

"memcell[addr[6:0]]"...

i think you should specify the full address range as index.i mean use 31:0 instead of 6:0.
 

i think this code got error on it .can anybody help on
 

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