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REQ: VCD (Value Change Dump) standard document

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the_penetrator

the_penetrator

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vcd value change dump

hi there

i am looking for VCD standard document! However i sense that it has not been standardized by IEEE. Probably any official doc (e.g. from Verilog engineers that pioneered VCD) would do.

PS: Is there any good parser tool for reading/writing VCD. I am also looking for formal docs (as above).

thanks in advance

the_penetrator©
 

value change dump standard

People!

I found that VCD formal description is in Chapter 18 of IEEE STD 1364-2001 (Verilog) document.

However, i have a question. How can i generate VCD from VHDL simulation??? Cause in Verilog you get to use PLI tasks.

Please direct me to some good parser/tool for VCD.

Thanks

the_penetrator©
 

This code must be added to each Verilog testbench in order for a VCD file to be generated.

// The following code will generate a VCD file containing
// all of the nets in the instance t.uut. "t" is the module name of the
// testfixture, "uut" is the instance name
// of the design being tested.

initial begin
$dumpfile("invchn26.vcd"); // Change filename as appropriate.
$dumpvars(1, t.uut);
end
 

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