cyboman
Member level 4
i have synthesized a very simple sequential circuit for an FPGA. i burned it and it worked fine but for some reason during implementation i got the following warning:
Route:455 - CLK Net:u0/q<17> may have excessive skew because
1 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
can anyone explain what does it mean? should i be worried? and if i should then how this can be avoided in the future?
any help is appreciated.
Route:455 - CLK Net:u0/q<17> may have excessive skew because
1 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
can anyone explain what does it mean? should i be worried? and if i should then how this can be avoided in the future?
any help is appreciated.