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  1. #1
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    How column decoder and row decoder works in SRAM memory?

    i am trying to understand memories , i may be completely wrong also.
    please help me with your comments.

    we use row and column decoders in memories.

    if i have 128 * 128 bit memory ( to maintain aspect ratio)
    i will have 14 bit address line.

    as per my understanding i will give 7 bit of address for row decoders and remaining 7 bits for column decoders.
    now my row decoder will enable word lines of a particular row and all 128 bit cells will get activated in that row.

    i am confused how will column decoder work here?

    do we activate a complete row , take all data from all bitlines and then choose right one using column decoder?
    do we first activate a row ,then further activate columns and read only that particular bit cell...

    i suppose option 2 should be correct , but i could not find any data on this

    please help

    •   Alt11th March 2010, 15:53



  2. #2
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    betwixt's Avatar
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    Re: sram memory basics

    It depends on the type of memory, some just use the intersection of the selected row and selected column. Some read a whole row or column into an internal buffer then select the individual item in the row with the other selector.

    How it works internally isn't particularly important, it is the fact that only one bit from one row and one column is accessed. If the memory is more than one bit wide, for example an 8-bit memory, there are effectively 8 identical 'planes' of memory cells, each having the same number of rows and columns and each selected simultaneously when addressed. One bit is written to or read from each plane giving the appearance of the data being 8-bits wide.

    That how it works in static memory. In dynamic memory, the same applies but normally to reduce the number of connections needed on the IC, the rows and columns are entered on the same pins. Usually the row number is entered first then the -RAS signal is activated to latch the row number into the chip, then the column address is put on the pins and the -CAS signal is activated to latch the column number into the chip. Inside the decoding works the same, it's just a way of being able to use larger numbers of rows and columns without running out of pins.


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